EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 164

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
The I
eZ80L92 system clock is f
f
In MASTER mode, the I
The use of two separately-programmable dividers allows the MASTER mode output fre-
quency to be set independently of the frequency at which the I
ture is particularly useful in multimaster systems because the frequency at which the I
bus is sampled must be at least 10 times the frequency of the fastest master on the bus to
ensure that START and STOP conditions are always detected. By using two programma-
ble clock divider stages, a high sampling frequency can be ensured while allowing the
MASTER mode output to be set to a lower frequency.
Bus Clock Speed
The I
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I
and the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I
MASTER mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].
Bit
Position
[6:3]
M
[2:0]
N
f
f
SAMP
SAMP
SCL
2
2
2
=
C clocks are derived from the eZ80L92’s system clock. The frequency of the
C bus is defined for bus clock speeds up to 100 Kbps (400 Kbps in FAST mode).
C sampling frequency is determined by the frequency of the eZ80L92 system clock
supplied by:
2
=
C bus at least ten times faster than the bus clock speed of the fastest master on the
10 • (M + 1)(2)
f
SCLK
2
N
f
SCLK
0000–1111
000–111
N
Value
2
C clock output frequency on SCL (f
SCK
. The I
Description
I
I
2
2
2
C bus is sampled by the I
C clock divider scalar value.
C clock divider exponent.
SCL
2
C bus is sampled. This fea-
2
C block at the frequency
Product Specification
) is supplied by:
I
2
C Serial I/O Interface
2
C must sam-
2
C in
2
C
158

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