EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 189

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

On-Chip Instrumentation
PS013014-0107
OCI Activation
On-Chip Instrumentation
debugging features. The OCI provides run control, memory and register visibility, com-
plex breakpoints, and trace history features.
The OCI employs all the functions of the ZiLOG Debug Interface (ZDI) as described in
the ZDI section. It also adds the following debug features:
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OCI has the following sections:
1. JTAG interface.
2. ZDI debug control.
3. Trace buffer memory.
4. Complex triggers.
The OCI features clock initialization circuitry so that external debug hardware can be
detected during power up. The external debugger must drive the OCI clock pin (TCK)
Low at least two system clock cycles prior to the end of the RESET to activate the OCI
block. If TCK is High at the end of the RESET, the OCI block shuts down so that it does
not draw power in normal product operation. When the OCI is shut down, ZDI is enabled
directly and can be accessed through the clock (TCK) and data (TDI) pins. For more infor-
mation on ZDI, see
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.
2. The eZ80L92 MCU does not contain the boundary scan register required for 1149.1 compliance.
Control through a 4-pin JTAG port that conforms to IEEE Standard 1149.1 (Test Ac-
cess Port and Boundary-Scan Architecture)
Complex break-point trigger functions.
Break-point enhancements, such as the ability to:
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Trace history buffer.
Software break-point instruction.
Define two break-point addresses that form a range.
Break on masked data values.
Start or stop trace.
Assert a trigger output signal.
ZiLOG Debug Interface
1
(OCI™) for the ZiLOG eZ80 CPU core enables powerful
on page 160.
2
.
Product Specification
On-Chip Instrumentation
eZ80L92 MCU
183