EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 40

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Low-Power Modes
PS013014-0107
SLEEP Mode
HALT Mode
The eZ80L92 MCU provides a range of power-saving features. The highest level of power
reduction is provided by SLEEP mode. The next level of power reduction is provided by
the HALT instruction. The lowest level of power reduction is provided by the clock
peripheral power-down registers.
Execution of the eZ80 CPU’s SLP instruction places the eZ80L92 MCU into SLEEP
mode. In SLEEP mode, the operating characteristics are:
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The eZ80 CPU can be brought out of SLEEP mode by any of the following operations:
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After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. See
Execution of the eZ80 CPU’s HALT instruction places the eZ80L92 MCU into HALT
mode. In HALT mode, the operating characteristics are:
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Primary crystal oscillator is disabled.
System clock is disabled.
eZ80 CPU is idle.
Program counter (PC) stops incrementing.
32 kHz crystal oscillator continues to operate and drives the Real-Time Clock and the
Watchdog Timer (if WDT is configured to operate from the 32 kHz oscillator.)
RESET through the external RESET pin driven Low.
RESET through a Real-Time Clock alarm.
RESET through a Watchdog Timer time-out (if running off of the 32 kHz oscillator and
configured to generate a RESET upon time-out).
RESET through execution of a Debug RESET command.
Primary crystal oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ80 CPU is idle.
Program counter stops incrementing.
Reset on page
33.
Product Specification
Low-Power Modes
34