EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 43

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit Position
7
PHI_OFF
6
5
PRT5_OFF
4
PRT4_OFF
3
PRT3_OFF
2
PRT2_OFF
1
PRT1_OFF
0
PRT0_OFF
Value
R/W
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
7
0
Description
PHI Clock output is disabled (output is high-impedance).
PHI Clock output is enabled.
Reserved.
System clock to PRT5 is powered down.
System clock to PRT5 is powered up.
System clock to PRT4 is powered down.
System clock to PRT4 is powered up.
System clock to PRT3 is powered down.
System clock to PRT3 is powered up.
System clock to PRT2 is powered down.
System clock to PRT2 is powered up.
System clock to PRT1 is powered down.
System clock to PRT1 is powered up.
System clock to PRT0 is powered down.
System clock to PRT0 is powered up.
R
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
Low-Power Modes
R/W
1
0
R/W
0
0
37