EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 49

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Port x Data Direction Registers
In addition to the other GPIO Control Registers, the Port x Data Direction Registers (see
Table
Table 8. Port x Data Direction Registers (PB_DDR = 009Bh, PC_DDR =
Port x Alternate Register 1
In addition to other GPIO Control Registers, the Port x Alternate Register 1 (see
control the operating modes of the GPIO port pins. See
Table 9. Port x Alternate Registers 1 (PB_ALT1 = 009Ch, PC_ALT1 = 00A0h,
Port x Alternate Register 2
In addition to other GPIO Control Registers, the Port x Alternate Register 2 (see
control the operating modes of the GPIO port pins. See
Table 10. Port x Alternate Registers 2 (PB_ALT2 = 009Dh, PC_ALT2 =
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Reset
CPU Access
Note: R/W = Read/Write.
8) control the operating modes of the GPIO port pins. See
PD_ALT1 = 00A4h)
009Fh, PD_DDR = 00A3h)
00A1h, PD_ALT2 = 00A5h)
R/W
R/W
R/W
7
0
7
0
7
1
R/W
R/W
R/W
6
1
6
0
6
0
R/W
R/W
R/W
5
1
5
0
5
0
R/W
R/W
R/W
4
1
4
0
4
0
Table
Table
R/W
R/W
R/W
3
1
3
0
3
0
6.
6.
General-Purpose Input/Output
Product Specification
Table
R/W
R/W
R/W
2
1
2
0
2
0
6.
eZ80L92 MCU
R/W
R/W
R/W
1
1
1
0
1
0
Table
Table
R/W
R/W
R/W
0
1
0
0
0
0
10)
9)
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