EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 51

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Table 12. Vectored Interrupt Operation
PS013014-0107
Memory
Mode
Z80 Mode
ADL
Bit
{MBASE[7:0], I[7:0], 1Eh} and {MBASE, I[7:0], 1Fh}. The least significant byte is
stored at the lower address.
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit
interrupt vector for the highest priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80L92 and is therefore not
visible externally. The response time of the eZ80 CPU to an interrupt request is a
function of the current instruction being executed as well as the number of WAIT states
being asserted.
The interrupt vector, {I[7:0], IVECT[7:0]}, is visible on the address bus, ADDR[15:0],
when the interrupt service routine begins. The response of the eZ80 CPU to a vectored
interrupt on the eZ80L92 is explained in
active until the Interrupt Service Routine (ISR) starts. We recommend you to change the
Interrupt Page Address Register (I) value from its default value of 00h as this address can
create conflicts between the non-maskable interrupt vector, the RST instruction addresses,
and the maskable interrupt vectors.
0
MADL
Bit
0
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
IEF1 ← 0
IEF2 ← 0
The starting Program Counter is effectively {MBASE, PC[15:0]}.
Push the 2-byte return address PC[15:0] on the ({MBASE,SPS}) stack.
The ADL mode bit remains cleared to 0.
The interrupt vector address is located at { MBASE, I[7:0], IVECT[7:0] }.
PC[15:0] ← ( { MBASE, I[7:0], IVECT[7:0] } ).
The ending Program Counter is effectively {MBASE, PC[15:0]}
The interrupt service routine must end with RETI.
Table
12. Interrupt sources are required to be
Product Specification
Interrupt Controller
eZ80L92 MCU
45