EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 54

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Chip Selects and Wait States
PS013014-0107
Memory and I/O Chip Selects
Memory Chip Select Operation
The eZ80L92 MCU generates four Chip Selects for external devices. Each Chip Select is
programmed to access either memory space or I/O space. The Memory Chip Selects can
be individually programmed on a 64 KB boundary. Each I/O Chip Select can choose a
256-byte section of I/O space. In addition, each Chip Select can be programmed for up to
7 wait states.
Each of the Chip Selects is enabled for either the memory address space or the I/O address
space, but not both. To select the memory address space for a particular Chip Select,
CSx_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular
Chip Select, CSx_IO must be set to 1. After RESET, the default is for all Chip Selects to
be configured for the memory address space. For either the memory address space or the
I/O address space, the individual Chip Selects must be enabled by setting CSx_EN
(CSx_CTL[3]) to 1.
Operation of each Memory Chip Selects is controlled by three control registers. To enable
a particular Memory Chip Select, following conditions must be fulfilled:
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If all the above conditions are met to generate a Memory Chip Select, then the following
actions occur:
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If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a
particular Chip Select is valid for a single 64 KB page.
The Chip Select is enabled by setting CSx_EN to 1.
The Chip Select is configured for Memory by clearing CSx_IO to 0.
The address is in the associated Chip Select range:
CSx
No higher priority (lower number) Chip Select meets the above conditions.
A memory access instruction must be executing.
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low).
MREQ is asserted (driven Low).
Depending upon the instruction, either RD or WR is asserted (driven Low).
_LBR[7:0] ≤ ADDR[23:16] ≤
CSx
_UBR[7:0]
Chip Selects and Wait States
Product Specification
eZ80L92 MCU
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