EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 56

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Table 13. Register Values for Memory Chip Select Example in Figure 4
PS013014-0107
Chip
Select
CS0
CS1
CS2
CS3
I/O Chip Select Operation
CSx_CTL[3]
CSx_EN
1
1
1
1
I/O Chip Selects are active when the CPU is performing I/O instructions. As the I/O space
is separate from the memory space in the eZ80L92 device, there can never be a conflict
between I/O and memory addresses.
The eZ80L92 MCU supports a 16-bit I/O address. The I/O Chip Select logic decodes the
High byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices is always accessed from within any memory
mode (ADL or Z80). The MBASE offset value used for setting the Z80 MEMORY mode
page is also always ignored.
Four I/O Chip Selects are available with the eZ80L92. To generate a particular I/O Chip
Select, the following conditions must be fulfilled:
•
•
•
•
•
•
The Chip Select is enabled by setting CSX_EN to 1.
The Chip Select is configured for I/O by setting CSx_IO to 1.
An I/O Chip Select address match occurs—ADDR[15:8] = CSx_LBR[7:0].
No higher-priority (lower-number) Chip Select meets the above conditions.
The I/O address is not within the on-chip peripheral address range
chip peripheral registers assume priority for all addresses where:
0080h ≤ ADDR[15:0] ≤ 00FFh
An I/O instruction must be executing.
CSx_CTL[4]
CSx_IO
0
0
0
0
CSx_LBR CSx_UBR Description
A0h
D0h
00h
00h
CFh
FFh
7Fh
9Fh
CS0 is enabled as a Memory Chip Select.
Valid addresses range from
000000h–7FFFFFh.
CS1 is enabled as a Memory Chip Select.
Valid addresses range from
800000h–9FFFFFh.
CS2 is enabled as a Memory Chip Select.
Valid addresses range from
A00000h–CFFFFFh.
CS3 is enabled as a Memory Chip Select.
Valid addresses range from
D00000h–FFFFFFh.
Chip Selects and Wait States
Product Specification
0080h
eZ80L92 MCU
–
00FFh
. On-
50