EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 59

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Table 14. Z80
PS013014-0107
STATE T1
STATE T2
STATE T3
Chip Selects During Bus Request/Bus Acknowledge Cycles
Bus Mode Controller
eZ80
Z80
®
The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated Chip Select signal is asserted.
During State T2, the RD signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one eZ80
system clock cycle prior to the end of State T2, additional WAIT states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered. The data is latched by the eZ80L92 at the rising
edge of the eZ80 system clock at the end of State T3.
®
®
Bus Mode
When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral then drives the address bus (and data bus). The CPU continues to gen-
erate Chip Select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80L92 MCU.
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80L92 to be configured to connect seamlessly with external eZ80, Z80, Intel-, or
Motorola-compatible devices. Bus modes for each of the chip selects can be configured
independently using the Chip Select Bus Mode Control Registers. The number of eZ80
system clock cycles per bus mode state is also independently programmable. For Intel bus
mode, multiplexed address and data can be selected in which the lower byte of the address
and the data byte both use the data bus, DATA[7:0]. Each of the bus modes is explained in
more detail in the following sections.
Chip selects configured for eZ80 Bus Mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown
in the
mode.
Chip selects configured for Z80 mode modify the Z80 bus signals to match the Z80
microprocessor address and data bus interface signal format and timing. During Read
operations, the Z80 Bus Mode employs three states (T1, T2, and T3) as described in
Table
Bus Mode
Bus Mode Read States
14.
AC Characteristics on page
203. The default mode for each chip select is eZ80s
Chip Selects and Wait States
Product Specification
WAIT
eZ80L92 MCU
) are asserted
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