EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 74

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
enabled) can be active. For I/O Chip Selects, this register defines the address to which
ADDR[15:8] is compared to generate an I/O Chip Select. All Chip Select lower bound
registers reset to
Table 22. Chip Select x Lower Bound Registers (CS0_LBR = 00A8h,
Bit
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSx_LBR
CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h)
00h–FFh For Memory Chip Selects (CSx_IO = 0)
00h
Value
.
R/W
7
0
0
0
0
Description
This byte specifies the lower bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in these
registers for determining whether a Memory Chip Select
signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the Chip Select address value.
ADDR[15:8] is compared to the values contained in these
registers for determining whether an I/O Chip Select signal
must be generated.
R/W
6
0
0
0
0
R/W
5
0
0
0
0
R/W
4
0
0
0
0
R/W
3
0
0
0
0
Chip Selects and Wait States
Product Specification
R/W
2
0
0
0
0
eZ80L92 MCU
R/W
1
0
0
0
0
R/W
0
0
0
0
0
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