EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 76

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
Chip Select x Control Registers
The Chip Select x Control register, detailed in
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is
registers is
Table 24. Chip Select x Control Registers (CS0_CTL = 00AAh, CS1_CTL =
Bit
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSx_WAIT*
4
CSx_IO
3
CSx_EN
[2:0]
Note: *These WAIT state settings apply only to the default eZ80 bus mode. See Table 25.
00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)
00h
.
Value
000
001
010
100
101
011
110
000
111
0
1
0
1
R/W
E8h
7
1
0
0
0
Description
0 WAIT states are asserted when this Chip Select is active.
1 WAIT state is asserted when this Chip Select is active.
2 WAIT states are asserted when this Chip Select is active.
3 WAIT states are asserted when this Chip Select is active.
4 WAIT states are asserted when this Chip Select is active.
5 WAIT states are asserted when this Chip Select is active.
6 WAIT states are asserted when this Chip Select is active.
7 WAIT states are asserted when this Chip Select is active.
Chip Select is configured as a Memory Chip Select.
Chip Select is configured as an I/O Chip Select.
Chip Select is disabled.
Chip Select is enabled.
Reserved.
, while the reset state for the 3 other Chip Select control
R/W
6
1
0
0
0
R/W
5
1
0
0
0
Table
R/W
24, enables the Chip Selects, specifies
4
0
0
0
0
R/W
3
1
0
0
0
Chip Selects and Wait States
Product Specification
R
2
0
0
0
0
eZ80L92 MCU
R
1
0
0
0
0
R
0
0
0
0
0
70

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