EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 88

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
Programmable Reload Timer Registers
Table 31. PRT Timer Out Operation Example (Continued)
Each programmable reload timer is controlled using five 8-bit registers. These registers
are the Timer Control register, Timer Reload Low Byte register, Timer Reload High Byte
register, Timer Data Low Byte register, and Timer Data High Byte register.
The Timer Control register can be read or written to. The timer reload registers are Write-
Only and are located at the same I/O address as the timer data registers, which are Read-
Only.
Timer Control Registers
The Timer Control register, described in
including enabling the timer, selecting the clock divider, enabling the interrupt, selecting
between CONTINUOUS and SINGLE PASS modes, and enabling the auto-reload feature.
Table 32. Timer Control Registers (TMR0_CTL = 0080h, TMR1_CTL = 0083h,
TMR2_CTL = 0086h, TMR3_CTL = 0089h, TMR4_CTL = 008Ch, or TMR5_CTL
= 008Fh)
Parameter
PRT Clock Divider = 4
CONTINUOUS Mode
PRT Reload Value
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
PRT_IRQ
Value
0
1
Description
The timer does not reach its end-of-count value. This bit is reset
to 0 every time the TMRx_CTL register is read.
The timer reaches its end-of-count value. If IRQ_EN is set to 1,
an interrupt signal is sent to the CPU. This bit remains 1 until the
TMRx_CTL register is read.
R
7
0
R/W
6
0
Control Register(s)
TMRx_CTL[3:2]
TMRx_CTL[4]
{TMRx_RR_H,
TMRx_RR_L}
Table
R/W
5
0
32, is used to control operation of the timer,
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
0003h
Value
00b
1
eZ80L92 MCU
R/W
1
0
R/W
0
0
82

Related parts for EZ80L92AZ050SG