MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 94
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 94 of 481
- Download datasheet (2Mb)
System Integration Block (SIB)
The user should not normally program more than one chip-select line to the same area.
When this occurs, the address compare logic will set address decode conflict (ADC) in the
system control register (SCR) and generate BERR if address decode conflict enable
(ADCE) is set. Only one chip-select line will be driven because of internal line priorities. CS0
has the highest priority, and CS3 the lowest. BERR will not be asserted on write accesses
to the chip-select registers.
If one chip select is programmed to be read-only and another chip select is programmed to
be write-only, then there will be no overlap conflict between these two chip selects, and the
ADC bit will not be set.
When a bus master attempts to write to a read-only location, the chip-select logic will set
write protect violation (WPV) in the SCR and generate BERR if write protect violation enable
(WPVE) is set. The CS line will not be asserted.
3-44
The chip-select logic is reset only on total system reset (asser-
tion of RESET and HALT). Accesses to the internal RAM and
registers, including the system configuration registers (BAR and
R/W
Figure 3-9. Chip-Select Block Diagram
CS0
CS1
CS2
MC68302 USER’S MANUAL
OPTION REGISTER 0 (OR0)
BASE REGISTER 0 (BR0)
CS3
COMPARE LOGIC
DTACK GENERATION
NOTE
CS0
CS1
CS2
CS3
DTACK
MOTOROLA
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