MC68060RC50 Freescale Semiconductor, MC68060RC50 Datasheet - Page 410
MC68060RC50
Manufacturer Part Number
MC68060RC50
Description
IC MPU 32BIT 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68060RC50
Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Price
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Part Number:
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Manufacturer:
MOTO
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LPSTOP
MC68060 Instructions
Condition Codes:
Instruction Format:
Instruction Fields:
D-20
Immediate field—Specifies the data to be loaded into the status register.
15
Set according to the immediate operand.
1
0
3. At the time of the bus cycle termination, (TA or TEA) the state of bus grant
4. After the broadcast cycle is complete the processor will load the immediate
5. Once the low-power stopped state has been entered, the internal processor
6. During entry into the low-power stopped state, the system bus must be quies-
14
1
0
determines how the processor will leave the system bus while in the low-power
stopped state. If the processor is granted the bus, it will drive the transfer
attributes, address bus, data bus, and most control signals high while in the
low-power stopped state. If the bus grant is removed from the processor, it will
threestate all threestateable signals of the system bus at the conclusion of the
bus write broadcast cycle.
operand into the SR and drive the PST lines signalling the low-power stopped
state has been entered.
clock is disabled (except to a small number of flip flops to support interrupt and
reset recognition) and all input signals except the RSTI and IPLx, may float.
The processor clock (CLK) input may be stopped during the low-power
stopped state for additional power saving. If this is done, CLK must be stopped
in the low state.
cent from the cycle after the broadcast cycle termination until the PST signals
indicate the low-power stopped state. During exit from the low-power stopped
state, the system bus must be quiescent and control signal inputs to the pro-
cessor negated, beginning with the cycle RSTI, or IPLx is asserted until the
PST signals indicate that the processor is in an exception processing state.
13
1
0
12
1
0
11
1
0
(MC68060, MC68LC060, MC68EC060)
10
0
0
M68060 USER’S MANUAL
Low-Power Stop
9
0
0
IMMEDIATE DATA
8
0
1
7
0
1
6
0
1
5
0
0
4
0
0
3
0
0
LPSTOP
2
0
0
1
0
0
MOTOROLA
0
0
0
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