GCIXP1250BB Intel, GCIXP1250BB Datasheet - Page 15

• Manufacturer Part Number: GCIXP1250BB
• Description: IC MPU NETWORK 200MHZ 520-BGA
• Manufacturer: Intel

Specifications of GCIXP1250BB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 520-BGA
• Pin Count: 520
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837412

Status:
10.
Problem:
Implication:
Workaround:
Status:
Specification Update
Note: The error will be corrected if EN_ECC_GEN is enabled (bit 3).
CTX_ARB[SRAM]
Example C - When the priority queue is used, both requests must use the
same queue.
Original code
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], priority, ctx_swap
Workaround 1
SRAM[WRITE, $x2, sAddr, 1, 2], priority
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], priority, ctx_swap
Workaround 2
SRAM[WRITE, $x1, sAddr, 0, 3], priority, sig_done
SRAM[UNLOCK, --, sAddr, 0, 1], priority
CTX_ARB[SRAM]
Example D – correctly handling the defer optional token.
Original code
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], ctx_swap, defer[1]
alu[$x3, --, b, r3]
Workaround 1
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
alu[$x3, --, b, r3]
SRAM[WRITE, $x2, sAddr, 1, 2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], ctx_swap
Workaround 2
alu[$x1, --, b, r1]
alu[$x2, --, b, r2]
alu[$x3, --, b, r3]
SRAM[WRITE, $x1, sAddr, 0, 3], sig_done
SRAM[UNLOCK, --, sAddr, 0, 1]
Ctx_arb[SRAM]
NoFix
ECC Single Bit Errors (Correctable Errors) Status Reporting Not Operational
Bits 16, 17, 18 and 24 (SA_ECC_ERR, PCI_ECC_ERR, UENG_ECC_ERR, ECC_INTR) in the
SDRAM_CSR register are not functional. They will always read back as "0".
The device cannot detect what block initiated the SDRAM read that resulted in an ECC error.
None.
Fixed
Intel
®
IXP1250 Network Processor
Errata
15