EZ80L92AZ050EG Zilog, EZ80L92AZ050EG Datasheet - Page 139
EZ80L92AZ050EG
Manufacturer Part Number
EZ80L92AZ050EG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3877
EZ80L92AZ050EG
EZ80L92AZ050EG
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PS013014-0107
SPI Baud Rate Generator
Data Transfer Procedure with SPI Configured as the Master
Write Collision
The WRITE COLLISION flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made
to write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing
the WCOL bit is performed by reading SPI_SR with the WCOL bit set.
The SPI’s Baud Rate Generator creates a lower frequency clock from the high-frequency
system clock. The Baud Rate Generator output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI’s Baud Rate Generator consists of a 16-bit downcounter, two 8-bit registers, and
associated decoding logic. The Baud Rate Generator’s initial value is defined by the two
BRG Divisor Latch registers, {SPI_BRG_H, SPI_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value
clock rising edge, the BRG reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and
outputs a pulse to indicate the end-of-count. Calculate the SPI Data Rate with the follow-
ing equation:
Upon RESET, the 16-bit BRG divisor value resets to
a Master, the BRG divisor value must be set to a value of
is operating as a Slave, the BRG divisor value must be set to a value of
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.
Follow the steps below for data transfer with SPI configured as the master:
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. External device must de-assert the SS pin if currently asserted.
3. Load the SPI Control Register, SPI_CTL.
4. Assert the ENABLE pin of the slave device using a GPIO pin.
5. Load the SPI Transmit Shift Register, SPI_TSR.
SPI Data Rate (bps)
=
2 X SPI Baud Rate Generator
System Clock Frequency
Divisor
0002h
0003h
. When the SPI is operating as
0001h
Product Specification
or greater. When the SPI
Serial Peripheral Interface
. On the next system
0004h
eZ80L92 MCU
or greater.
133
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