MPC8540PX667LC Freescale Semiconductor, MPC8540PX667LC Datasheet - Page 9

• Manufacturer Part Number: MPC8540PX667LC
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
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Multiple-cycle execution unit (MU)
— Four-cycle latency for integer and floating-point multiplication (including integer, fractional, and both
— Variable-latency divide: 4, 11, 19, and 35 cycles for all Book E, SPE, and SPFP divide instructions. Note
— Four-cycle floating-point multiply
— Four-cycle floating-point add and subtract
Signal processing engine APU (SPE APU). The SIMD capability provided by the 64-bit execution units
(MIU, LSU, SIU1) is not a separate execution unit. The hardware that executes 32-bit Book E instructions
also executes the lower half of 64-bit SPU instructions.
— Single-cycle integer add and subtract
— Single-cycle logical operations
— Single-cycle shift and rotate
— Four-cycle integer pipelined multiplies
— 4-, 11-, 19-, and 35-cycle integer divides
— Four-cycle single instruction multiple data (SIMD) pipelined multiply-accumulate (MAC)
— 64-bit accumulator for MAC operations
— Single-precision floating-point operations
Load/store unit (LSU)
— Three-cycle load latency
— Fully pipelined
— Four-entry load queue allows up to four load misses before stalling
— Can continue servicing load hits when load queue is full
— Six-entry store queue allows full pipelining of stores
Cache coherency
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)
— High-speed, on-chip local bus with data tagging
— 32-bit address bus
— 60x-like address protocol with address pipelining and retry/copyback
— Two general-purpose read data, one write data bus
— 128-bit data plus parity/tags (each data bus)
— Supports out-of-order reads, in-order writes
— Little to no data bus arbitration logic required for native systems
— Easily adaptable to 60x-like environments
— Supports one-level pipelining of addresses with address-retry responses
Extended exception handling
— Supports Book E interrupt model
vector and scalar floating-point multiply instructions).
that the MU allows divide instructions to bypass the second two MU pipeline stages, freeing those
stages for other MU instructions to execute in parallel.
– Interrupt vector prefix register (IVPR)
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
MPC8540 Architecture Overview
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