MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 112

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

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cycle, the M68040 ignores all TA and TEA assertions while MI is asserted; when RSTI is
asserted, MI is asserted.
5.6 ARBITRATION SIGNALS
The following control signals support requests to an external arbiter to become the bus
master. Refer to Section 7 Bus Operation for detailed information about the relationship
of the arbitration signals to bus operation.
BR
5.6.1 Bus Request (
)
This output signal indicates to the external arbiter that the processor needs to become bus
master for one or more bus transfers. BR is negated when the M68040 begins an access
to the external bus with no other accesses pending, and BR remains negated until another
access is required. There are some situations in which the M68040 asserts BR and then
negates it without having run bus transfers; this is a disregard request condition. Refer to
Section 7 Bus Operation for details about this state.
BG
5.6.2 Bus Grant (
)
This input signal from an external arbiter indicates that the bus is available to the M68040
as soon as the current bus access completes. BG must be asserted and BB must be
negated (indicating the bus is free) before the M68040 assumes ownership of the bus.
BB
5.6.3 Bus Busy (
)
This three-state bidirectional signal indicates that the bus is currently owned. B B is
monitored as a processor input to determine when a alternate bus master has released
control of the bus. BG must be asserted and BB must be negated (indicating the bus is
free) before the M68040 asserts BB as an output to assume ownership of the bus. The
processor keeps BB asserted until the external arbiter negates BG and the processor
completes the bus transfer in progress. When releasing the bus, the processor negates
BB , then sets it to a high-impedance state for use again as an input.
5.7 PROCESSOR CONTROL SIGNALS
The following signals control disabling caches and memory management units (MMUs)
and support processor and external device initialization.
CDIS
5.7.1 Cache Disable (
)
CDIS dynamically disables the on-chip caches on the next internal cache access
boundary. CDIS does not flush the data and instruction caches; entries remain unaltered
and become available after CDIS is negated. The assertion of CDIS does not affect
snooping. During a processor reset, the level on CDIS is latched and used to select the
normal bus mode (CDIS high) or multiplexed bus mode (CDIS low). Refer to Section 4
Instruction and Data Caches for information about the caches and to Section 7 Bus
Operation for information about the multiplexed bus mode. Refer to Appendix E
5-10
M68040 USER’S MANUAL
MOTOROLA
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