MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 190

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

The M68040 can be in the active bus cycle, park, or implicit ownership states when BG is
negated. Depending on the state the processor is in when BG is negated, uncertain
conditions can occur. The only guaranteed time that the processor relinquishes the bus is
when BG is negated prior to the rising edge of BCLK in which the last TA or TEA is
asserted and the processor is in the active bus cycle state. However, if the processor is in
either the active bus cycle, park, or implicit ownership states and BG is negated at the
same time or after the last TA or TEA is asserted, then from the standpoint of the external
bus arbiter, the next action that the processor takes is undetermined because the
processor can internally decide to perform another active bus cycle (indeterminate
condition).
External bus arbiters must consider this indeterminate condition when negating BG and
must be designed to examine the state of BB immediately after negating BG to determine
whether or not the processor will run another bus cycle. A somewhat dangerous situation
exists when the processor begins a locked transfer after the bus has been granted to the
alternate bus master, causing the alternate bus master to perform a bus transfer during a
locked sequence. To correct this situation, the external bus arbiter must be able to
recognize the possible indeterminate condition and reassert BG to the processor when the
processor begins a locked sequence. The indeterminate condition is most significant when
dealing with systems that cannot allow locked transfers to be broken. Figure 7-31
illustrates an example of an error condition that is a consequence of the interaction
between the indeterminate condition and a locked transfer. External bus arbiters must be
designed so that all bus grants to all bus masters be nagated for at least one rising edge
of BCLK between bus tenures; preventing bus conflicts resulting from the above
conditions.
7-48
Asserted
Asserted
Asserted
Negated
Negated
BB
Asserted
Asserted
Asserted
Negated
Negated
BG
Table 7-6. M68040 Bus Arbitration States
Freescale Semiconductor, Inc.
Alternate Bus Master Ownership
For More Information On This Product,
Implicit Ownership
Active Bus Cycle
M68040 USER’S MANUAL
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State
Park
Idle
M68040 three-states BB; arbiter negates
BG; bus is not driven.
M68040 three-states BB; arbiter asserts
BG; bus is driven with undefined values.
M68040 asserts BB; arbiter asserts BG;
bus is driven with defined values;
TIP is asserted.
M68040 asserts BB; arbiter asserts BG;
bus is driven with undefined values; TIP is
asserted.
M68040 three-states BB; arbiter asserts
BG; M68040 does not drive the bus.
Conditions
MOTOROLA