MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 222

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

that caused the trap is also saved. Instruction execution resumes at the address in the
exception vector after the required instruction is prefetched.
8.2.4 Illegal Instruction and Unimplemented Instruction Exceptions
An illegal instruction exception corresponds to vector number 4, and occurs when the
processor attempts to execute an illegal instruction. An illegal instruction is an instruction
that contains any bit pattern that does not correspond to the bit pattern of a valid M68040
instruction. An illegal instruction exception is also taken after a breakpoint acknowledge
bus cycle is terminated, either by the assertion of the transfer acknowledge (TA) or the
transfer error acknowledge (TEA) signal. An illegal instruction exception can also be a
MOVEC instruction with an undefined register specification field in the first extension
word.
Instruction word patterns with bits 15–12 equal to $A do not correspond to legal
instructions for the M68040 and are treated as unimplemented instructions. $A word
patterns are referred to as an unimplemented instruction with A-line opcodes. When the
processor attempts to execute an unimplemented instruction with an A-line opcode, an
exception is generated with vector number 10, permitting efficient emulation of
unimplemented instructions. For instruction word patterns with bits 15–12 equal to $F refer
to Section 9 Floating-Point Unit (MC68040 Only).
Exception processing for illegal and unimplemented instructions is similar to that for
instruction traps. When the processor has identified an illegal or unimplemented
instruction, it initiates exception processing instead of attempting to execute the
instruction. The processor copies the SR, enters the supervisor mode, and clears T1 and
T0, disabling further tracing. The processor generates the vector number, either 4 or 10,
according to the exception type. The illegal or unimplemented instruction vector offset,
current PC, and copy of the SR are saved on the supervisor stack, with the saved value of
the PC being the address of the illegal or unimplemented instruction. Instruction execution
resumes at the address contained in the exception vector. It is the responsibility of the
exception handling routine to adjust the stacked PC if the instruction is emulated in
software or is to be skipped on return from the exception handler.
8.2.5 Privilege Violation Exception
To provide system security, some instructions are privileged. An attempt to execute one of
the following privileged instructions while in the user mode causes a privilege violation
exception:
Exception processing for privilege violations is similar to that for illegal instructions. When
the processor identifies a privilege violation, it begins exception processing before
MOTOROLA
ANDI to SR
CINV
CPUSH
EORI to SR
FRESTORE
Freescale Semiconductor, Inc.
FSAVE
MOVE from SR
MOVE to SR
MOVE USP
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
MOVEC
MOVES
ORI to SR
PFLUSH
STOP
PTEST
RESET
RTE
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