MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 228

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
Figure 8-4 illustrates a flowchart for interrupt exception processing. When processing an
interrupt exception, the processor first makes an internal copy of the SR, sets the mode to
supervisor, suppresses tracing, and sets the processor interrupt mask level to the level of
the interrupt being serviced. The processor attempts to obtain a vector number from the
interrupting device using an interrupt acknowledge bus cycle with the interrupt level
number output on the transfer modifier signals. For a device that cannot supply an
interrupt vector, the autovector signal (AVEC) must be asserted. In this case, the M68040
uses an internally generated autovector, which is one of vector numbers 25–31, that
corresponds to the interrupt level number (see Table 8-1). If external logic indicates a bus
error during the interrupt acknowledge cycle, the interrupt is considered spurious, and the
processor generates the spurious interrupt vector number, 24.
Once the vector number is obtained, the processor saves the exception vector offset, PC
value, and the internal copy of the SR on the active supervisor stack. The saved value of
the PC is the logical address of the instruction that would have been executed had the
interrupt not occurred.
If the M-bit of the SR is set, the processor clears the M-bit and creates a throwaway
exception stack frame on top of the interrupt stack as part of interrupt exception
processing. This second frame contains the same PC value and vector offset as the frame
created on top of the master stack, but has a format number of $1. The copy of the SR
saved on the throwaway frame has the S-bit set, the M-bit clear, and the interrupt mask
level set to the new interrupt level. It may or may not be set in the copy saved on the
master stack. The resulting SR (after exception processing) has the S-bit set and the M-bit
cleared. The processor loads the address in the exception vector into the PC, and normal
instruction execution resumes after the required prefetches for the interrupt handler
routine.
Most M68000 family peripherals use programmable interrupt vector numbers as part of
the interrupt acknowledge operation for the system. If this vector number is not initialized
after reset and the peripheral must acknowledge an interrupt request, the peripheral
usually returns the vector number for the uninitialized interrupt vector, 15.
MOTOROLA
M68040 USER’S MANUAL
8- 15
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