MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 261

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

The inclusion of the NAN data type in the IEEE floating-point number system requires
each conditional test to include the NAN condition code bit in its Boolean equation.
Because a comparison of a NAN with any other data type is unordered (i.e., it is
impossible to determine if a NAN is bigger or smaller than an in-range number), the
compare instruction sets the NAN condition code bit when an unordered compare is
attempted. All arithmetic instructions also set the FPCC NAN bit if the result of an
operation is a NAN. The conditional instructions interpret the NAN condition code bit equal
to one as the unordered condition.
The IEEE 754 standard defines four conditions: equal to (EQ), greater than (GT), less
than (LT), and unordered (UN). In addition, the standard only requires the generation of
the condition codes as a result of a floating-point compare operation. The FPU tests for
these conditions and 28 others at the end of any operation affecting the condition codes.
For purposes of the floating-point conditional branch, set byte on condition, decrement
and branch on condition, and trap on condition instructions, the MC68040 logically
combines the four FPCC bits to form 32 conditional tests. The 32 conditional tests are
separated into two groups—16 that cause an exception if an unordered condition is
present when the conditional test is attempted, IEEE nonaware tests, and 16 that do not
cause an exception, IEEE aware tests. The set of IEEE nonaware tests is best used:
An unordered condition occurs when one or both of the operands in a floating-point
compare operation is a NAN. The inclusion of the unordered condition in floating-point
branches destroys the familiar trichotomy relationship (greater than, equal, less than) that
exists for integers. For example, the opposite of floating-point branch greater than (FBGT)
is not floating-point branch less than or equal (FBLE). Rather, the opposite condition is
floating-point branch not greater than (FBNGT). If the result of the previous instruction was
unordered, FBNGT is true; whereas, both FBGT and FBLE would be false since
unordered fails both of these tests (and sets BSUN). Compiler programmers should be
MOTOROLA
• when porting a program from a system that does not support the IEEE 754 standard
• when generating high-level language code that does not support IEEE floating-point
to a conforming system or
concepts (i.e., the unordered condition).
Table 9-7. Floating-Point Condition Code Encodings
+ Normalized or Denormalized
– Normalized or Denormalized
+ 0
– 0
+ Infinity
– Infinity
+ NAN
– NAN
Freescale Semiconductor, Inc.
Data Type
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
N
0
1
0
1
0
1
0
1
Z
0
0
1
1
0
0
0
0
0
0
1
1
0
0
I
0
0
NAN
0
0
0
0
1
1
0
0
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