MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 275

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
The CMDREG1B field of the floating-point state frame can be used to determine the
instruction that caused of the OPERR exception. Note that CMDREG1B could be any of
the instructions listed in Table 9-11. If the destination is a floating-point data register, this
exception handler needs to supply the contents. If the destination is memory, the effective
address is supplied in the format $3 stack frame. If the destination is an integer data
register, the FPIAR points to the F-line instruction word that contains the integer data
register number. To exit the user OPERR exception handler, the saved floating-point
frame need not be restored and can be discarded prior to execution of the RTE
instruction.
9.7.4 Overflow
An overflow exception is detected for arithmetic operations in which the destination is a
floating-point data register or memory when the intermediate result’s exponent is greater
than or equal to the maximum exponent value of the selected rounding precision.
Overflow can only occur when the destination is in the single-, double-, or extended-
precision format; all other data format overflows are handled as operand errors. At the end
of any operation that could potentially overflow, the intermediate result is checked for
underflow, rounded, and then checked for overflow before it is stored to the destination. If
overflow occurs, the OVFL bit is set in the FPSR EXC byte.
Even if the intermediate result is small enough to be represented as an extended-
precision number, an overflow can occur. The intermediate result is rounded to the
selected precision, and the rounded result is stored in the extended-precision format. If the
magnitude of the intermediate result exceeds the range of the selected rounding precision
format, an overflow occurs.
9.7.4.1 MASKABLE EXCEPTION CONDITIONS. There are no conditions.
9.7.4.2 NONMASKABLE EXCEPTION CONDITIONS. When the OVFL bit is set in the
FPSR EXC byte as a result of a floating-point instruction, the processor always takes a
nonmaskable overflow exception. If the destination is a floating-point data register, then
the register is not affected, and either a pre-instruction or a post-instruction exception is
reported. If the destination is a memory or integer data register, an undefined result is
stored, and a post-instruction exception is taken immediately. Execution begins at the
M68040FPSP OVFL exception handler.
The values defined in Table 9-12 are stored in the destination based on the rounding
mode defined in the FPCR MODE byte. The M68040FPSP OVFL exception handler
rounds the result according to the rounding precision defined in the FPCR MODE byte if
the destination is a floating-point data register. If the destination is in memory or an integer
data register, then the rounding precision in the FPCR MODE byte is ignored, and the
given destination format defines the rounding precision. If the instruction has a forced
rounding precision (e.g., FSADD, FDMUL), the instruction defines the rounding precision.
The M68040FPSP OVFL exception handler then checks to see if the user OVFL
exception handler is enabled.
MOTOROLA
M68040 USER’S MANUAL
9- 31
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