MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 283

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

9.8 FLOATING-POINT STATE FRAMES
All floating-point arithmetic exception handlers must have FSAVE as the first floating-point
instruction; any other floating-point instruction causes another exception to be reported.
Once the FSAVE instruction has executed, the exception handler should use only the
FMOVEM instruction to read or write to the floating-point data registers since FMOVEM
cannot generate further exceptions or change the FPCR.
The FPU executes an FSAVE instruction to save the current floating-point internal state
for context switches and floating-point exception handling. When an FSAVE is executed,
the processor waits until the FPU either completes execution of all current instructions or
is unable to perform further processing due to a pending exception that must be serviced.
Any exceptions generated during this time are not reported and are saved in the resulting
busy state frame.
Four state frames can be generated as a result of an FSAVE instruction: busy, null, idle,
and unimplemented floating-point instruction. When an unimplemented floating-point
exception occurs, the FSAVE generates a 26-word unimplemented instruction state frame.
When an unsupported data type exception occurs, the FSAVE generates a 50-word busy
state frame. All floating-point arithmetic exceptions causes the FSAVE to generate either
the 26-word unimplemented instruction state frame or the 50-word busy state frame. For a
hardware reset or an FRESTORE of a null state frame, the FSAVE instruction generates a
null state frame. This null state frame is generated until the first nonconditional floating-
point instruction is executed (conditionals include FNOP, FBcc, FDBcc, FScc, and
FTRAPcc). Floating-point conditional instructions do not set an internal flag, which
changes the state frame from null to idle. If these instructions are the only ones executed
after a reset or an FRESTORE of a null state frame, then when FSAVE is executed, it
stacks a null state frame instead of an idle state frame. Note that this function is different
from that of the MC68881 and MC68882, and software must be aware of this difference if
compatibility with the MC68881 and MC68882 is desired. Once a nonconditional floating-
point instruction is executed, an FSAVE generates an idle state frame. The idle state
frame is generated whenever the FPU has no exceptions pending. An idle state frame is
saved if no exceptions are pending and at least one instruction has been executed since
the last hardware reset or FRESTORE of a null state frame. A 26-word unimplemented
floating-point instruction state frame is saved if the last instruction was an unimplemented
floating-point instruction. Figure 9-10 illustrates each of these state frames, followed by
definitions for each of the fields listed in alphabetical order.
MOTOROLA
The notation [XX–XX] indicates the length of the field but does
not indicate the field’s actual location. [XX, XX–XX] indicates
that one bit of the field is located separately or termed
differently from the other bits. This notation is for convenience
of explanation only. For example, WBTM [65–34] indicates that
WBTM is 32 bits long and gives a reference to each bit in
WBTM without giving its actual location in the state frame. For
the actual locations refer to Figure 9-10.
Freescale Semiconductor, Inc.
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M68040 USER’S MANUAL
NOTE
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