MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 36

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MOTOROLA
DIVU, DIVUL
EORI to CCR
DIVS, DIVSL
EORI to SR
Opcode
CPUSH
CMPM
CMPA
CMP2
BTST
CAS2
CHK2
CINV
CMPI
DBcc
EORI
CAS
CHK
CMP
EOR
CLR
–(bit number of Destination) ø Z;
CAS Destination – Compare Operand ø cc;
if Z, Update Operand ø Destination
else Destination ø Compare Operand
CAS2 Destination 1 – Compare 1 ø cc;
if Z, Destination 2 – Compare ø cc;
if Z, Update 1 ø Destination 1;
else Destination 1 ø Compare 1;
If Dn < 0 or Dn > Source
If Rn < LB or If Rn > UB
If supervisor state
else TRAP
0 ø Destination
Destination – Source ø cc
Destination – Source
Destination – Immediate Data
Destination – Source ø cc
Compare Rn < LB or Rn > UB
If supervisor state
else TRAP
If condition false
Destination
Destination
Source
Immediate Data
Source
If supervisor state
else TRAP
Update 2 ø Destination 2
Destination 2 ø Compare 2
then TRAP
then TRAP
then invalidate selected cache lines
and Set Condition Codes
then if data cache push selected dirty data
cache lines; invalidate selected cache lines
then (Dn–1 ø Dn;
then Source
Table 1-4. Instruction Set Summary (Continued)
If Dn
then PC + d n ø PC)
Destination ø Destination
CCR ø CCR
Freescale Semiconductor, Inc.
–1
Source ø Destination
Source ø Destination
For More Information On This Product,
SR ø SR
Destination ø Destination
Operation
Go to: www.freescale.com
M68040 USER’S MANUAL
BTST Dn,<ea>
BTST #<data>,<ea>
CAS Dc,Du,<ea>
CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–(Rn2)
CHK <ea>,Dn
CHK2 <ea>,Rn
CINVL <caches>, (An)
CINVP <caches>, (An)
CINVA <caches>
CMP <ea>,Dn
CMPA <ea>,An
CMPM (Ay)+,(Ax)+
CMP2 <ea>,Rn
CPUSHL <caches>, (An)
CPUSHP <caches>, (An)
CPUSHA <caches>
DBcc Dn,<label>
DIVS.L <ea>,Dq
DIVS.L <ea>,Dr:Dq
DIVSL.L <ea>,Dr:Dq
DIVU.L <ea>,Dq
DIVU.L <ea>,Dr:Dq
DIVUL.L <ea>,Dr:Dq
EORI #<data>,CCR
EORI #<data>,SR
CLR <ea>
CMPI #<data>,<ea>
DIVS.W <ea>,Dn
DIVU.W <ea>,Dn
EOR Dn,<ea>
EORI #<data>,<ea>
Syntax
32
32
64
32
32 16 ø 16r:16q
32 32 ø 32q
64 32 ø 32r:32q
32 16 ø 16r:16q
32 ø 32r:32q
32 ø 32q
32 ø 32r:32q
32 ø 32r:32q
1- 15

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