MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 408

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
their related encodings. Note that the least significant bit of the instruction (bit 0) is the first
bit to be shifted into the instruction shift register.
C.6.1.1 EXTEST. The external test instruction (EXTEST) selects the boundary scan
register. This instruction also activates one internal function that is intended to protect the
device from potential damage while performing boundary scan operations. EXTEST
asserts internal reset for the MC68040V and MC68EC040V system logic to force a
predictable benign internal state.
C.6.1.2 HIGHZ. The HIGHZ instruction is an optional instruction provided as a Motorola
public instruction to anticipate the need to backdrive output pins during circuit board
testing. The HIGHZ instruction asserts internal system reset, selects the bypass register,
and forces all output and bidirectional pins to the high-impedance state.
Holding TMS high and clocking TCK for at least five rising edges causes the TAP
controller to enter the test-logic-reset state. Using only the TMS and TCK pins and the
capture-IR and update-IR states invokes the HIGHZ instruction. This scheme works
because the value captured by the instruction shift register during the capture-IR state is
identical to the HIGHZ opcode.
C.6.1.3 SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction provides two separate
functions. First, it provides a means to obtain a sample system data and control signal.
Sampling occurs on the rising edge of TCK in the capture-DR state. The user can observe
the data by shifting it through the boundary scan register to output TDO using the shift-DR
state. Both the data capture and the shift operations are transparent to system operation.
The user must provide some form of external synchronization to achieve meaningful
results since there is no internal synchronization between TCK and BCLK.
The second function of the SAMPLE/PRELOAD instruction is to initialize the boundary
scan register output cells before selecting EXTEST or CLAMP, which is accomplished by
ignoring data being shifted out of TDO while shifting in initialization data. The update-DR
state can then be used to initialize the boundary scan register and ensure that known data
and output state will occur on the outputs after entering the EXTEST or CLAMP
instruction.
C.6.1.4 CLAMP. The CLAMP instruction allows the state of the signals driven from the
MC68040V and MC68EC040V pins to be determined from the boundary scan register,
C-12
Bit 2
0
0
0
1
1
1
Bit 1
0
0
1
0
1
1
Table C-3. IEEE Standard 1149.1A Instructions
Bit 0
0
1
0
0
0
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Instruction Selected
SAMPLE/PRELOAD
M68040 USER’S MANUAL
Go to: www.freescale.com
PRIVATE
EXTEST
BYPASS
CLAMP
HIGHZ
Test Data Register Accessed
Boundary Scan
Boundary Scan
Bypass
Bypass
Bypass
MOTOROLA

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