MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 55

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
CM—Cache Mode
W—Write Protect
3.1.4 MMU Status Register
The MMUSR is a 32-bit register that contains the status information returned by execution
of the PTEST instruction. The PTEST instruction searches the translation tables to
determine status information about the translation of a specified logical address. Transfers
to and from the MMUSR are long-word transfers. The fields of the MMUSR are defined
following Figure 3-6, which illustrates the MMUSR.
Physical Address
B—Bus Error
G—Global
U1, U0—User Page Attributes
3-6
31
This field selects the cache mode and access serialization as follows:
Section 4 Instruction and Data Caches provides detailed information on caching
modes, and Section 7 Bus Operation provides information on serialization.
This bit indicates if the transparent block is write protected. If set, write and read-modify-
write accesses are aborted as if the resident bit in a table descriptor were clear.
This 20-bit field contains the upper bits of the translated physical address. Merging
these bits with the lower bits of the logical address forms the actual physical address.
Bit 12 is undefined if a PTEST is executed with 8-Kbyte pages selected.
The B-bit is set if a transfer error is encountered during the table search for the PTEST
instruction. If the B-bit is set, all other bits are zero.
This bit is set if the G-bit is set in the page descriptor.
These bits are set if corresponding bits in the page descriptor are set.
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
0 = Read and write accesses permitted
1 = Write accesses not permitted
PHYSICAL ADDRESS
Figure 3-6. MMU Status Register Format
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER'S MANUAL
Go to: www.freescale.com
12
11
B
10
G
U1 U 0
9
8
7
S
6
C M
5
M
4
O
3
MOTOROLA
W
2
1
T
R
0

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