MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 936
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
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MC68MH360 Product Brief
Figure D-4 shows that the QUICC32 time-slot assigner can support two TDM buses. Each
TDM bus can be of a different format—for example, one TDM can be a T1 line, and one can
be a CEPT line. Also this technique could be used to bridge frames from basic rate ISDN to
a T1/CEPT line, etc.
The QUICC32 can route channels to and from the QMC protocol to the two different TDM
buses in any combination.
Figure D-5 shows a TDM application having one line termination device that extracts clocks
and frame sychronization pulses. For T1/E1 line termination, devices exist that perform this
function. Alternatively, this can be achieved by a DSP from the Motorola 56K family.
For line termination the QUICC32 is capable of handling up to 32 channels and it may be
sufficient to omit the block labeled “Other PCM line devices”. If it is desired to incorporate
other PCM line devices in the system as shown in Figure D-5, the QUICC32 can provide
strobe signals to other devices that do not have a built-in time slot assigner.
D-6
NOTE: Two TDM buses may be simultaneously supported
ANY COMBINATION OF SCCs
CONNECTED TO ANY TDM.
SCC
SCC
SCC
SCC
SMC
SMC
AND SMCs MAY BE
with the time slot assigner.
Figure D-3. Serial Channel to TDM Bus Implementation
QUICC
NOTE: Independent receive and transmit clocking, routing,
Figure D-4. Dual TDM Bus Implementation
ASSIGNER
ANY COMBINATION OF SCCs
SLOT
CONNECTED TO THE TDM.
TIME
Freescale Semiconductor, Inc.
SCC
SCC
SCC
SCC
SMC
SMC
For More Information On This Product,
AND SMCs MAY BE
and syncs are supported.
QUICC
MC68360 USER’S MANUAL
Go to: www.freescale.com
ASSIGNER
SLOT
TIME
TDM BUS 1
TDM BUS 2
TIME DIVISION MULTIPLEXED BUS
T1, CEPT, IDL, GCI, ISDN,
PRIMARY RATE,
USER-DEFINED
(E.g. 32 channels HDLC
(E.g. ISDN basic rate with
remaining SCC’s and SMC’s
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