MC68340PV16VE Freescale Semiconductor, MC68340PV16VE Datasheet - Page 136

• Manufacturer Part Number: MC68340PV16VE
• Description: IC MCU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340PV16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

***************************************************************************
* Initialization code
***************************************************************************
* Start Chip Select Initialization:
INIT340
***************************************************************************
* Set up default module base address value
***************************************************************************
* Set up system protection register:
* Software watchdog disabled, double bus fault monitor disabled, bus
* monitor BERR after 16 clocks.
***************************************************************************
* Clock synthesizer control register:
* Switch from 8.3 to 16.7 MHZ
***************************************************************************
* Module configuration register:
* When FREEZE is asserted, software watchdog and periodic interrupt timer
* are disabled, bus monitor is enabled. Port B = 4 IRQs, 4 chip selects.
* Show Cycles enabled, external arbitration enabled. Supervisor/user
* SIM registers unrestricted, Interrupt Arbitration at priority $F
***************************************************************************
* Now, set up Address masks and base addresses for the chip selects:
LOOP
MOTOROLA
MOVEQ.L
MOVEC.L
MOVE.L
MOVES.L
MOVE.B
MOVE.W
MOVE.W
LEA
MOVEQ
LEA
MOVE.L
DBRA
MOVE.W
D0,DFC
#7,D0
#MODBASE+1,D0
D0,MBAR
#6,SYPCR+MODBASE
#$7F00,SYNCR+MODBASE
#$420F,MCR+MODBASE
CSAM0+MODBASE,A0 Point to CS0 addr. mask location.
#7,D
CSAM0$,A1
D0,LOOP
(A1)+,(A0)+
Freescale Semiconductor, Inc.
For More Information On This Product,
#$2700,SR
MC68340 USER’S MANUAL
Go to: www.freescale.com
write to MBAR
Init SR - interrupts masked
MBAR is in CPU space
load DFC to indicate CPU space
Set address/valid bit
Set up a loop counter.
Point to addr mask memory location.
Init. addr mask and base addr reg
X-bit doubles the default speed
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