MC68HC000EI8R2 Freescale Semiconductor, MC68HC000EI8R2 Datasheet - Page 137
MC68HC000EI8R2
Manufacturer Part Number
MC68HC000EI8R2
Description
IC MPU 16BIT 8MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC000IEI16.pdf
(189 pages)
Specifications of MC68HC000EI8R2
Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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9.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION
Table 9-16 lists the timing data for the jump (JMP), jump to subroutine (JSR), load
effective address (LEA), push effective address (PEA), and move multiple registers
(MOVEM) instructions. The total number of clock periods, the number of read cycles, and
the number of write cycles are shown in the previously described format.
JMP
JSR
LEA
PEA
MOVEM
M
MOVEM
R
MOVES
M
MOVES
R
9.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 9-17 lists the timing data for multiprecision instructions. The numbers of clock
periods include the times to fetch both operands, perform the operations, store the results,
9-10
Instruction
*The size of the index register (Xn) does not affect the instruction's execution time.
n is the number of registers to move.
M
M
R
R
Table 9-16. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times
EXECUTION TIMES
Byte/
Byte/
Word
Word
Word
Word
Long
Long
Long
Long
Size
—
—
—
—
Bcc
BRA
BSR
DBcc
Instruction
(3+2n/0)
16 (2/2)
12 (1/2)
(3+n/0)
18 (3/0)
22 (4/0)
18 (2/1)
22 (2/2)
12+4n
24+8n
8(2/0)
4(1/0)
(2/2n)
8+4n
8+8n
(An)
(2/n)
Table 9-15. Conditional Instruction Execution Times
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
(3+2n/0)
(3+n/0)
20 (3/0)
24 (4/0)
20 (2/1)
24 (2/2)
12+4n
12+8n
(An)+
Freescale Semiconductor, Inc.
—
—
—
—
—
—
—
—
For More Information On This Product,
Displacement
20 (3/0)
24 (4/0)
20 (2/1)
24 (2/2)
–(An)
(2/2n)
8+4n
8+8n
(2/n)
cc false
—
—
—
—
—
—
—
—
cc true
Word
Word
Word
Byte
Byte
Byte
Go to: www.freescale.com
(d 16 ,An)
(4+2n/0)
10 (2/0)
18 (2/2)
16 (2/2)
(4+n/0)
20 (4/0)
24 (5/0)
20 (3/1)
24 (3/2)
16+4n
16+8n
12+4n
12+8n
8(2/0)
(3/2n)
(3/n)
Branch Taken
(d 8 ,An,Xn)+
(4+2n/0)
14 (3/0)
22 (2/2)
12 (2/0)
20 (2/2)
(4+n/0)
24 (4/0)
28 (5/0)
24 (3/1)
28 (3/2)
18+4n
18+8n
14+4n
14+8n
(3/2n)
10(2/0)
10(2/0)
10(2/0)
10(2/0)
18(2/2)
18(2/2)
10(2/0)
(3/n)
—
(4+2n/0)
(xxx) W
10 (2/0)
18 (2/2)
16 (2/2)
(4+n/0)
20 (4/0)
24 (5/0)
20 (3/1)
24 (3/2)
16+4n
16+8n
12+4n
12+8n
8(2/0)
(3/2n)
(3/n)
Branch Not Taken
(5+2n/0)
(xxx).L
12 (3/0)
20 (3/2)
12 (3/0)
20 (3/2)
(5+n/0)
24 (5/0)
28 (6/0)
24 (4/1)
28 (4/2)
20+4n
20+8n
16+4n
16+8n
(4/2n)
(4/n)
10(2/0)
10(2/0)
16(3/0)
6(1/0)
—
—
—
—
(4+2n/0)
(d 8 PC)
10 (2/0)
18 (2/2)
16 (2/2)
(4+n/0)
16+4n
16+8n
8(2/0)
—
—
—
—
(d 16 , PC, Xn)*
MOTOROLA
(4+2n/0)
(4+n/0)
14 (3/0)
22 (2/2)
12 (2/0)
20 (2/2)
18+4n
18+8n
—
—
—
—
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