PCF8584P,112 NXP Semiconductors, PCF8584P,112 Datasheet - Page 11

• Manufacturer Part Number: PCF8584P,112
• Description: IC CTRL PARALLEL/I2C BUS 20-DIP
• Manufacturer: NXP Semiconductors

Specifications of PCF8584P,112

• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Type: Parallel Bus to I²C Bus Controller
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 1.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 4.5 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3532-5; 935069300112; PCF8584PN

Philips Semiconductors
6.8.1.5
These bits control the generation of the I
generation of repeated START condition, and generation of the STOP condition (see Table 7).
Table 6 Register access control; ESO = 1 (serial interface on) and ES1 = 1; long-distance (4-wire) mode; note 1
Note
1. Trying to read from or write to registers other than S0 and S1 (setting ESO = 0) brings the PCF8584 out of the
Table 7 Instruction table for serial bus control
Notes
1. In master receiver mode, the last byte must be terminated with ACK bit HIGH (‘negative acknowledge’).
2. If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by a START
3. All other STA and STO mode combinations not mentioned in Table 7 are NOPs.
6.8.1.6
This bit must be set normally to a logic 1. This causes the I
each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic 0) when the I
operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a
negative acknowledge on the I
6.8.2
The read-only section of S1 enables access to I
1997 Oct 21
I
2
long-distance mode.
condition + address will be generated. This allows ‘chaining’ of transmissions without relinquishing bus control.
C-bus controller
STA
A0
1
1
0
1
1
0
1
0
R
EGISTER
STA and STO
ACK
S1
INTERNAL REGISTER ADDRESSING: LONG-DISTANCE (4-WIRE) MODE
STATUS SECTION
STO
ES1
1
1
1
0
0
1
1
0
2
C-bus, which halts further transmission from the slave device.
PRESENT
MST/REC;
MST/TRM
MST/TRM
2
SLV/REC
C-bus START condition and transmission of slave address and R/W bit,
MODE
MST
ANY
ES2
X
X
X
2
C-bus status information; see Table 4.
STOP WRITE
STOP READ;
FUNCTION
CHAINING
2
11
C-bus controller to send an acknowledge automatically after
REPEAT
START
START
IACK
DATA
NOP
X
X
1
W S1: control
R S1; status
R/W S0; (data)
transmit START + address, remain
MST/TRM if R/W = 0;
go to MST/REC if R/W = 1
same as for SLV/REC
transmit STOP go to SLV/REC mode; note 1
send STOP, START and address after last
master frame without STOP sent; note 2
no operation; note 3
OPERATION
FUNCTION
2
C-bus controller is
Product specification
PCF8584