ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet
ISP1161ABD-S
Specifications of ISP1161ABD-S
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ISP1161ABD-S Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - Philips ...
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ISP1161A Full-speed Universal Serial Bus single-chip host and device controller Rev. 03 — 23 December 2004 1. General description The ISP1161A is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of ...
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Philips Semiconductors PC (host) USB I/F Fig 1. ISP1161A operating as a USB device. EMBEDDED SYSTEM µP DSC Fig 2. ISP1161A operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161A operating as both USB ...
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Philips Semiconductors 2. Features ■ Complies with Universal Serial Bus Specification Rev. 2.0 ■ The Host Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161A supports ...
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... Table 1: Ordering information Type number Package Name Description plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm ISP1161ABD LQFP64 plastic low profile quad flat package; 64 leads; body 7 × 7 × 1.4 mm ISP1161ABM LQFP64 9397 750 13962 Product data Full-speed USB single-chip host and device controller Rev. 03 — ...
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Philips Semiconductors 5. Block diagram 9397 750 13962 Product data Full-speed USB single-chip host and device controller Rev. 03 — 23 December 2004 ISP1161A © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
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Philips Semiconductors POWER-ON RESET µP interface DMA HANDLER Host bus I/F µP HANDLER Fig 5. Host controller sub-block diagram. POWER-ON RESET DMA HANDLER Device µP HANDLER BUS I/F bus I/F EP HANDLER Fig 6. Device controller sub-block diagram. 9397 750 ...
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... Fig 7. Pin configuration LQFP64. 6.2 Pin description Table 2: Symbol DGND 9397 750 13962 Product data Full-speed USB single-chip host and device controller ISP1161ABD ISP1161ABM Pin description for LQFP64 [1] Pin Type Description 1 - digital ground 2 I/O bit 2 of bidirectional data; slew-rate controlled; TTL input; ...
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Philips Semiconductors Table 2: Symbol D6 D7 DGND D8 D9 D10 D11 D12 D13 DGND D14 D15 DGND V hold1 n. hold2 DREQ1 DREQ2 DACK1 9397 750 13962 Product data Full-speed USB single-chip host and device ...
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Philips Semiconductors Table 2: Symbol DACK2 INT1 INT2 TEST RESET NDP_SEL EOT DGND D_SUSPEND D_WAKEUP GL D_VBUS H_WAKEUP CLKOUT H_SUSPEND XTAL1 XTAL2 9397 750 13962 Product data Full-speed USB single-chip host and device controller Pin description for LQFP64 …continued [1] ...
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Philips Semiconductors Table 2: Symbol DGND H_PSW1 H_PSW2 D_DM D_DP H_DM1 H_DP1 H_DM2 H_DP2 H_OC1 H_OC2 V CC AGND V reg(3. n.c. DGND D0 D1 [1] Symbol names with an overscore (e.g. NAME) represent active LOW signals. 9397 ...
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Philips Semiconductors 7. Functional description 7.1 PLL clock multiplier A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external ...
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Philips Semiconductors 7.6 GoodLink Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration, the LED indicator will blink on momentarily. When the DC has been successfully enumerated (the device address is set), the ...
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Philips Semiconductors Figure 9 ISP1161A. The ISP1161A provides two DMA channels: • DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer between a microprocessor’s system memory and ISP1161A HC internal FIFO buffer RAM • DMA channel ...
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Philips Semiconductors Figure 10 ISP1161A internal control registers. When the microprocessor accesses the HC. When the microprocessor accesses the DC. Fig 10. A microprocessor accessing via an automux switch. ...
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Philips Semiconductors Fig 12. 16-bit register access cycle. Most of the ISP1161A internal control registers are 16 bits wide. Some of the internal control registers have 32-bit width. register is accessed. The complete cycle of accessing a 32-bit register consists ...
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Philips Semiconductors CS A1 15:0 ] Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO buffer ...
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Philips Semiconductors 8.5 FIFO buffer RAM access by DMA mode The DMA interface between a microprocessor and the ISP1161A is shown in Figure When doing a DMA transfer, at the beginning of every burst the ISP1161A outputs a DMA request ...
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Philips Semiconductors DREQ DACK 15:0 ] data #1 data #K EOT N = 1/2 byte count of transfer data number of cycles/burst. Fig 18. DMA transfer in burst mode. In Figure 17 HIGH ...
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Philips Semiconductors Fig 19. Interrupt pin operating modes. 8.6.2 HC’s interrupt output pin (INT1) To program the four configuration modes of the HC’s interrupt output signal (INT1), set bits InterruptPinTrigger and InterruptOutputPolarity of the HcHardwareConfiguration register (20H - read, A0H ...
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Philips Semiconductors HcInterruptEnable register MIE RHSC FNO group 2 RHSC FNO HcInterruptStatus register Fig 20. HC interrupt logic. There are two groups of interrupts represented by group 1 and group 2 in ...
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Philips Semiconductors To re-enable the interrupt generation: 1. Set all bits in the HcµPInterrupt register. 2. Set bit InterruptPinEnable to logic 1. Remark: Bit InterruptPinEnable in the HcHardwareConfiguration register latches the interrupt output. When this bit is set to logic ...
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Philips Semiconductors In isochronous mode, an interrupt is issued upon each packet transaction. The firmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the ...
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Philips Semiconductors Event A (see with bit INTENA set to logic 0, an interrupt will not be generated at pin INT2. However, it will be registered in the corresponding DcInterrupt register bit. Event B (see because bit SOF in the ...
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Philips Semiconductors 9. USB host controller (HC) 9.1 HC’s four USB states The ISP1161A USB HC has four USB states − USBOperational, USBReset, USBSuspend, and USBResume − that define the HC’s USB signaling and bus states responsibilities. USBOperational USBOperational write ...
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Philips Semiconductors Reset HC state = USBOperational Initialize HC Entry Fig 24. ISP1161A HC USB transaction loop The USB traffic blocks are: • Reset This includes hardware reset by pin RESET and software reset by the HcSoftwareReset command (A9H). The ...
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Philips Semiconductors The physical storage media of PTD data for the HCD is the microprocessor’s system RAM. For the ISP1161A HC, the storage media is the internal FIFO buffer RAM. The HCD prepares PTD data in the microprocessor system RAM ...
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Philips Semiconductors 9.3.1 PTD data header definition The PTD forms the header of the PTD data. It tells the HC the transfer type, where the payload data goes, and the payload data’s actual size. A PTD byte ...
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Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD CompletionCode[3:0] R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 ...
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Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access DirectionPID[1: B5_5 R/W This bit is logic 0 at power-on reset. When this feature is not used, software used for ISP1161A is the ...
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Philips Semiconductors • ATL buffer length = 400H, ITL buffer length = 200H. This is insufficient use of the internal FIFO buffer RAM. • ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO ...
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Philips Semiconductors The data transfer can be done via the PIO mode or the DMA mode. The data transfer rate can Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes are supported. Multi-cycle burst modes of ...
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Philips Semiconductors Fig 28. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation and C program example Figure 29 mode. The ISP1161A provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the ...
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Philips Semiconductors 1 Host bus I 000H 001H 3FFH ITL0 buffer RAM (8-bit width) Fig 29. PIO access to internal FIFO buffer RAM. Following is an example program that shows how to write data into ...
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Philips Semiconductors However, if communication with a peripheral USB device is desired, the device should be connected to the downstream port and pass enumeration. // The example program for writing ATL buffer RAM #include <conio.h> #include <stdio.h> #include <dos.h> // ...
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Philips Semiconductors // Write 80 (0x50) bytes of data into ATL buffer RAM for (i=0;i<wCount;i++) { outport(HcDataPort,PTDData[i]); }; // Check EOT interrupt bit wData = HcRegRead(wHcuPInterrupt); printf("\n HC Interrupt Status = %xH.\n",wData); // Check Buffer status register wData = HcRegRead(wHcBufferStatus); ...
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Philips Semiconductors end of the frame for full-speed and low-speed packets. By programming these fields, the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers (HcITLBufferLength, 2AH - read, AAH - write) is programmed. In ...
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Philips Semiconductors 9.5.1 Time domain behavior In example 1 download a scenario before the next interrupt. Note that on the ISO interrupt of frame N: • The ISO packet for frame will be written • The AT ...
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Philips Semiconductors (frame N) Fig 32. HC time domain behavior: example 3. 9.5.2 Control transaction limitations The different phases of a Control transfer (SETUP, Data and Status) should never be put in the same ATL. 9.6 Microprocessor loading The maximum ...
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Philips Semiconductors Using either internal or external 15 kΩ resistors. Fig 33. Use of 15 kΩ pull-down resistors on downstream ports. 9.8 OC detection and power switching control A downstream port provides 5 V power supply to V hardware functions ...
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Philips Semiconductors 9.8.1 Using an internal OC detection circuit The internal OC detection circuit can be used only when power supply. The HCD must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, to logic 1. An ...
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Philips Semiconductors 9.8.2 Using an external OC detection circuit When V internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Regardless of the V always be used. To use an external OC detection ...
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Philips Semiconductors XOSC_6MHz XOSC (to DC PLL VOLTAGE REGULATOR DC_EnableClock Fig 37. ISP1161A suspend and resume clock scheme. In suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and ...
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Philips Semiconductors Under the USBSuspend state, once pin H_WAKEUP goes HIGH, after 160 µs, the internal clock will be up. If pin H_WAKEUP continues to be HIGH, then the internal clock will be kept running, and the microprocessor can set ...
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Philips Semiconductors Table 7: HC registers summary Address (Hex) Register read write 00 - HcRevision 01 81 HcControl 02 82 HcCommandStatus 03 83 HcInterruptStatus 04 84 HcInterruptEnable 05 85 HcInterruptDisable 0D 8D HcFmInterval 0E - HcFmRemaining 0F - HcFmNumber 11 ...
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Philips Semiconductors Table 8: HcRevision register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R R Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 ...
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Philips Semiconductors Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol HCFS[1:0] Reset 0 0 Access R/W R/W Table 11: Bit 10.1.3 HcCommandStatus ...
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Philips Semiconductors the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the HC without concern for corrupting previously issued commands. The HCD has normal read access to all ...
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Philips Semiconductors Table 13: Bit 10.1.4 HcInterruptStatus register (R/W: 03H/83H) This register provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the ...
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Philips Semiconductors Bit 7 6 Symbol reserved RHSC Reset 0 0 Access R/W R/W Table 15: Bit 10.1.5 HcInterruptEnable register (R/W: 04H/84H) Each enable bit in the HcInterruptEnable register corresponds ...
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Philips Semiconductors Table 16: HcInterruptEnable register: bit allocation Bit 31 30 Symbol MIE Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit ...
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Philips Semiconductors writing logic bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged read, the current value of the HcInterruptEnable register is returned. Code (Hex): 05 — read Code (Hex): 85 ...
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Philips Semiconductors 10.2 HC frame counter registers 10.2.1 HcFmInterval register (R/W: 0DH/8DH) The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the ...
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Philips Semiconductors 10.2.2 HcFmRemaining register (R: 0EH) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Code (Hex): 0E — read Table 22: HcFmRemaining register: bit allocation Bit 31 30 Symbol FRT ...
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Philips Semiconductors Table 24: HCFmNumber register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R R Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 ...
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Philips Semiconductors Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 27: Bit 10.3 HC Root Hub registers All registers included in ...
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Philips Semiconductors 10.3.1 HcRhDescriptorA register (R/W: 12H/92H) The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are Implementation-Specific (IS). The descriptor length (11), descriptor type and hub controller current (0) fields ...
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Philips Semiconductors Table 29: Bit 10.3.2 HcRhDescriptorB register (R/W: 13H/93H) The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are ...
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Philips Semiconductors Code (Hex): 13 — read Code (Hex): 93 — write Table 30: HcRhDescriptorB register: bit allocation Bit 31 30 Symbol Reset N/A N/A Access R R Bit 23 22 Symbol Reset N/A N/A Access R R Bit 15 ...
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Philips Semiconductors Table 31: Bit 10.3.3 HcRhStatus register (R/W: 14H/94H) The HcRhStatus register is divided into two parts. The lower word of a DWORD represents the Hub Status field and the upper word represents ...
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Philips Semiconductors Table 33: Bit 9397 750 13962 Product data Full-speed USB single-chip host and device controller HcRhStatus register: bit description Symbol Description CRWE On write—ClearRemoteWakeupEnable: Writing logic ...
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Philips Semiconductors 10.3.4 HcRhPortStatus[1:2] register (R/W [1]:15H/95H, [2]: 16H/96H) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is ...
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Philips Semiconductors Table 35: Bit 9397 750 13962 Product data Full-speed USB single-chip host and device controller HcRhPortStatus[1:2] register: bit description Symbol Description PSSC PortSuspendStatusChange: This bit is set when the full resume ...
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Philips Semiconductors Table 35: Bit 9397 750 13962 Product data Full-speed USB single-chip host and device controller HcRhPortStatus[1:2] register: bit description Symbol Description PPS (read) PortPowerStatus: This bit reflects the port power status, regardless ...
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Philips Semiconductors Table 35: Bit 9397 750 13962 Product data Full-speed USB single-chip host and device controller HcRhPortStatus[1:2] register: bit description Symbol Description PSS (read) PortSuspendStatus: This bit indicates whether the port is suspended or in the ...
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Philips Semiconductors 10.4 HC DMA and interrupt control registers 10.4.1 HcHardwareConfiguration register (R/W: 20H/A0H) 1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit should be used together with the register HcµPInterruptEnable to enable pin INT1. ...
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Philips Semiconductors Table 37: Bit 10.4.2 HcDMAConfiguration register (R/W: 21H/A1H) Code (Hex): 21 — read Code (Hex): A1 — write Table 38: HcDMAConfiguration register: bit allocation Bit 15 14 Symbol Reset 0 0 ...
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Philips Semiconductors Table 39: Bit 10.4.3 HcTransferCounter register (R/W: 22H/A2H) This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the ...
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Philips Semiconductors 10.4.4 HcµPInterrupt register (R/W: 24H/A4H) All the bits in this register will be active on power-on reset. However, none of the active bits will cause an interrupt on the interrupt pin (INT1) unless they are set by the ...
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Philips Semiconductors Table 43: Bit 1 0 10.4.5 HcµPInterruptEnable register (R/W: 25H/A5H) The bits 6:0 in this register are the same as those in the HcµPInterrupt register. They are used together with bit 0 of the HcHardwareConfiguration register to enable ...
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Philips Semiconductors Table 45: Bit 10.5 HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1161A silicon chip. The high byte stands for the product name ...
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Philips Semiconductors 10.5.2 HcScratch register (R/W: 28H/A8H) This register is for the HCD to save and restore values when required. Code (Hex): 28 — read Code (Hex): A8 — write Table 48: HcScratch register: bit allocation Bit 15 14 Symbol ...
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Philips Semiconductors 10.6 HC buffer RAM control registers 10.6.1 HcITLBufferLength register (R/W: 2AH/AAH) Write to this register to assign the ITL buffer size in bytes: ITL0 and ITL1 are assigned the same value. For example, if HcITLBufferLength register is set ...
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Philips Semiconductors Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 55: Bit 10.6.3 HcBufferStatus register (R: 2CH) Code (Hex): 2C — read Table 56: HcBufferStatus register: bit allocation Bit 15 14 Symbol Reset 0 ...
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Philips Semiconductors 10.6.4 HcReadBackITL0Length register (R: 2DH) This register’s value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before ...
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Philips Semiconductors 10.6.6 HcITLBufferPort register (R/W: 40H/C0H) This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte that comes ...
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Philips Semiconductors Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 65: Bit The HCD must set the byte count into the HcTransferCounter register and check the HcBufferStatus register before reading from or writing to ...
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Philips Semiconductors 11. USB device controller (DC) The Device Controller (DC) in the ISP1161A is based on the Philips ISP1181B USB Full-Speed Interface Device IC. The functionality, commands, and register sets are the same as ISP1181B in 16-bit bus mode. ...
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Philips Semiconductors • The SIE also checks for the device number and endpoint number and verifies whether they are acceptable. • If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus register. If the endpoint is empty, ...
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Philips Semiconductors A DMA transfer is terminated when any of the following conditions are met: • The DMA count is complete • DMAEN = 0 • The DMA controller asserts EOT. When the DMA transfer is terminated, the buffer is ...
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Philips Semiconductors • Endpoint enable bit (FIFOEN) • Size bits of an enabled endpoint (FFOSZ[3:0]) • Isochronous bit of an enabled endpoint (FFOISO). Remark: Register changes that affect the allocation of the shared FIFO storage among endpoints must not be ...
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Philips Semiconductors 11.3.4 Endpoint initialization In response to the standard USB request, Set Interface, the firmware must program all 16 ECRs of the ISP1161A’ sequence (see endpoints are enabled or not. The hardware will then automatically allocate FIFO ...
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Philips Semiconductors 11.4 Suspend and resume 11.4.1 Suspend conditions The ISP1161A DC detects a USB suspend status when a constant idle state is present on the USB bus for more than 3 ms. The bus-powered devices that are suspended must ...
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Philips Semiconductors A USB BUS INT_N GOSUSP WAKEUP SUSPEND Fig 38. Suspend and resume timing. In Figure • A: indicates the point at which the USB bus enters the idle state. • B: indicates resume condition, which can be a ...
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Philips Semiconductors 11.4.2 Resume conditions A wake-up from the suspend state is initiated either by the USB host or by the application: • USB host: drives a K-state on the USB bus (global resume) • Application: remote wake-up through a ...
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Philips Semiconductors 12. DC DMA transfer Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without intervention of the Central Processor Unit (CPU). Many different implementations of DMA exist. The ...
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Philips Semiconductors Table 70: Endpoint identifier 12.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the DcHardwareConfiguration register (see shown in Table 71: Symbol DREQ2 DACK2 EOT RD WR The DMA subsystem of ...
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Philips Semiconductors The following example shows the steps which occur in a typical DMA transfer: 1. ISP1161A’s DC receives a data packet in one of its endpoint FIFOs; the packet must be transferred to memory address 1234H. 2. ISP1161A’s DC ...
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Philips Semiconductors Table 72: Symbol EOT DACK-only mode ISP1161A’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address ...
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Philips Semiconductors the DcDMACounter register. When the internal counter completes the transfer as programmed in the DcDMACounter, an EOT condition is generated and the DMA operation stops. Short packet: before any DMA transfer takes place. When a short packet has ...
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Philips Semiconductors 13. DC commands and registers The functions and registers of ISP1161A’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and ...
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Philips Semiconductors Table 75: DC command and register summary Name Data flow commands Write Control OUT Buffer Write Control IN Buffer Write Endpoint n Buffer ( 14) Read Control OUT Buffer Read Control IN Buffer Read Endpoint ...
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Philips Semiconductors Table 75: DC command and register summary Name Read Endpoint n Error Code ( 14) Unlock Device Write/Read DcScratch register Read Frame Number Read Chip ID Read DcInterrupt register [1] With N representing the number ...
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Philips Semiconductors Table 77: Bit 13.1.2 DcAddress register (R/W: B7H/B6H) This command is used to set the USB assigned address in the DcAddress register and enable the USB device. The DcAddress register bit ...
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Philips Semiconductors Table 80: DcMode register: bit allocation Bit 7 6 Symbol DMAWD reserved [1] Reset 0 0 Access R/W R/W [1] Unchanged by a bus reset. Table 81: Bit 13.1.4 DcHardwareConfiguration ...
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Philips Semiconductors Bit 7 6 Symbol DAKOLY DRQPOL Reset 0 1 Access R/W R/W Table 83: Bit 9397 750 13962 Product data Full-speed USB single-chip ...
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Philips Semiconductors 13.1.5 DcInterruptEnable register (R/W: C3H/C2H) This command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). That is, ...
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Philips Semiconductors Bit 15 14 Symbol IEP6 IEP5 Reset 0 0 Access R/W R/W Bit 7 6 Symbol reserved SP_IEEOT Reset 0 0 Access R/W R/W Table 85: Bit ...
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Philips Semiconductors Table 87: Bit For selecting an endpoint for device DMA transfer, see 13.1.7 DcDMACounter register (R/W: F3H/F2H) This command accesses the DcDMACounter register. The bit ...
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Philips Semiconductors Table 89: Bit 13.1.8 Reset Device (F6H) This command resets the ISP1161A DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): ...
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Philips Semiconductors Table 90: Word # 0 (lower byte) 0 (upper byte) 1 (lower byte) 1 (upper byte) … DIV 2 Table 91 … Remark: There is no protection against ...
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Philips Semiconductors Table 93: Bit 13.2.3 Stall Endpoint/Unstall Endpoint (40H–4FH/80H—8FH) These commands are used to stall or unstall an endpoint. The commands modify the content of the DcEndpointStatus register (see A stalled ...
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Philips Semiconductors 13.2.5 Clear Endpoint Buffer (70H, 72H–7FH) This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception of new packets. Reception of a complete packet causes the Buffer Full fl OUT endpoint ...
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Philips Semiconductors 13.2.7 Acknowledge Setup (F4H) This command acknowledges to the host that a SETUP packet was received. The arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The ...
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Philips Semiconductors Table 98: Error code (Binary) 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 13.3.2 Unlock Device (B0H) This command unlocks ISP1161A’s DC from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are ...
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Philips Semiconductors Code (Hex): B2/B3 — write/read Scratch register Transaction — write/read 1 word Table 101: DcScratch register: bit allocation Bit 15 14 Symbol reserved Reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Access R/W ...
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Philips Semiconductors Table 105: Example of DcFrameNumber register access 13.3.5 Read Chip ID (R: B5H) This command reads the chip identification code and hardware version number. The firmware must check this information to determine the supported functions ...
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Philips Semiconductors Table 108: DcInterrupt register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R R Bit 23 22 Symbol EP14 EP13 Reset 0 0 Access R R Bit 15 14 Symbol EP6 EP5 Reset 0 0 Access ...
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Philips Semiconductors 14. Power supply ISP1161A can operate at either 3.3 V. When using ISP1161A’s power supply input, only V connected to the 5 V power supply. An application with power ...
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Philips Semiconductors 15. Crystal oscillator and LazyClock The ISP1161A has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in signal of 6 MHz can be applied to input XTAL1, while leaving output ...
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Philips Semiconductors hardware configuration register CLKRUN SUSPEND . . . CLKDIV [ 3 NOLAZY Fig 47. Oscillator and LazyClock logic. When ISP1161A’s DC enters ‘suspend’ state (by setting and clearing bit GOSUSP in the DcMode register), ...
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Philips Semiconductors 16. Limiting values Table 110: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage to V pin CC(5V supply voltage to V CC(3.3V) reg(3.3) V input voltage ...
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Philips Semiconductors 17. Static characteristics Table 112: Static characteristics; supply pins Symbol Parameter internal regulator output reg(3.3) I operating ...
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Philips Semiconductors Table 114: Static characteristics: analog I/O pins (D+, D− Symbol Parameter Input levels V differential input sensitivity DI V differential common mode CM ...
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Philips Semiconductors 18. Dynamic characteristics Table 115: Dynamic characteristics Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency XTAL ...
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Philips Semiconductors 18.1 Programmed I/O timing • If you are accessing only the HC, then the HC Programmed I/O timing applies. • If you are accessing only the DC, then the DC Programmed I/O timing applies. • If you are ...
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Philips Semiconductors 15 data D [ 15:0 ] valid Fig 49. HC Programmed interface timing. 18.1.2 DC Programmed I/O timing Table 118: Dynamic characteristics: DC Programmed interface timing Symbol Parameter Read ...
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Philips Semiconductors Table 118: Dynamic characteristics: DC Programmed interface timing Symbol Parameter t chip deselect time after WR HIGH WHSH t data set-up time before WR HIGH DVWH t data hold time after WR HIGH WHDZ A0 (2) CS/DACK2 RD ...
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Philips Semiconductors 18.2 DMA timing 18.2.1 HC single-cycle DMA timing Table 119: Dynamic characteristics: HC single-cycle DMA timing Symbol Parameter Read/write timing t RD pulse width RLRH t read process data set-up time RLDV t read process data hold time ...
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Philips Semiconductors 18.2.2 HC burst mode DMA timing Table 120: Dynamic characteristics: HC burst mode DMA timing Symbol Parameter Read/write timing (for 4-cycle and 8-cycle burst mode) t WR/RD LOW pulse width RLRH t WR/RD HIGH to next WR/RD LOW ...
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Philips Semiconductors 18.2.3 External EOT timing for HC single-cycle DMA Fig 54. External EOT timing for HC single-cycle DMA. 18.2.4 External EOT timing for HC burst mode DMA Fig 55. External EOT timing for HC burst mode DMA. 18.2.5 DC ...
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Philips Semiconductors 18.2.6 DC single-cycle DMA read timing in DACK-only mode Table 122: Dynamic characteristics: DC single-cycle DMA read timing in DACK-only mode Symbol Parameter t DREQ off after DACK on ASRP t DACK pulse width ASAP ...
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Philips Semiconductors 18.2.8 EOT timing in DC single-cycle DMA Table 124: Dynamic characteristics: EOT timing in DC single-cycle DMA Symbol Parameter t input RD/WR HIGH after DREQ RSIH on t DACK off after input RD/WR IHAP HIGH t EOT pulse ...
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Philips Semiconductors DREQ2 (1) DACK2 (1) Programmable polarity: shown as active LOW. Fig 60. DC burst mode DMA timing. 18.2.10 EOT timing in DC burst mode DMA Table 126: Dynamic characteristics: EOT timing in DC burst mode ...
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Philips Semiconductors 19. Application information 19.1 Typical interface circuit + 3.3 V SH7709 CS5 RD RD/WR DREQ0 DACK0 DREQ1 DACK1 + 5 V CLKOUT EXTAL ...
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Philips Semiconductors • RD and WR are common read and write signals. These signals are active LOW. • There are two DMA channel standard control lines: – DREQ1 and DACK1 – DREQ2 and DACK2 (in each case one channel is ...
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Philips Semiconductors MECHANISM CONTROL TASK IMAGE PROCESSING TASKS FILE MANAGEMENT PRINTER UI/CONTROL OS DEVICE DRIVERS MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER HOST STACK RISC ROM ISP1161A RAM LEN CONTROL Fig 63. ISP1161A software model for DSC application. 20. Test ...
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Philips Semiconductors 21. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the ...
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Philips Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A ...
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Philips Semiconductors 22. Soldering 22.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – ...
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Philips Semiconductors [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± ...
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Philips Semiconductors 23. Revision history Table 128: Revision history Rev Date CPCN Description 03 20041223 200412020 Product data (9397 750 13962) Modifications: • Section 9.4.1 the internal FIFO buffer RAM” • Section 9.8.1 “Using an internal OC detection sentence, changed ...
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Philips Semiconductors 24. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...
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Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . ...