PIC32MX795F512H-80I/PT Microchip Technology Inc., PIC32MX795F512H-80I/PT Datasheet - Page 71
PIC32MX795F512H-80I/PT
Manufacturer Part Number
PIC32MX795F512H-80I/PT
Description
512KB Flash, 128KB RAM, 80 MHz, USB, ENET, 2xCAN, 8 DMA
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC32MX795F512H-80IPT.pdf
(254 pages)
Specifications of PIC32MX795F512H-80I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
64-pin TQFP
Programmable Memory
512K Bytes
Ram Size
128K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
MICROCHIP
Quantity:
218
Company:
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TABLE 4-8:
Legend:
Note
0600 T1CON
0610
0620
0800 T2CON
0810
0820
0A00 T3CON
0A10
0A20
0C00 T4CON
0C10
0C20
0E00 T5CON
0E10
0E20
1:
2:
TMR1
TMR2
TMR3
TMR4
TMR5
PR1
PR2
PR3
PR4
PR5
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
These bits are not available on 64-pin devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
TIMER1-TIMER5 REGISTER MAP
31/15
ON
ON
ON
ON
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TWDIS
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
TWIP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR1<15:0>
TMR2<15:0>
TMR3<15:0>
TMR4<15:0>
TMR5<15:0>
PR1<15:0>
PR2<15:0>
PR3<15:0>
PR4<15:0>
PR5<15:0>
Bits
TGATE
TGATE
TGATE
TGATE
TGATE
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCKPS<2:0>
TCKPS<2:0>
TCKPS<2:0>
TCKPS<2:0>
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCKPS<1:0>
20/4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
19/3
T32
T32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSYNC
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCS
TCS
TCS
TCS
17/1
TCS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
for more
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
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