PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 63

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PIC12F683-I/SN

Manufacturer Part Number
PIC12F683-I/SN
Description
8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12F683-I/SN

A/d Inputs
4-Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
5
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin SOIC-N
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
9.0
The
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
FIGURE 9-1:
9.1
When configuring and using the ADC the following
functions must be considered:
• GPIO configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
9.1.1
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding GPIO
section for more information.
© 2006 Microchip Technology Inc.
Note:
Analog-to-Digital
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
ADC Configuration
GPIO CONFIGURATION
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
GP1/AN1/V
ADC BLOCK DIAGRAM
GP0/AN0
GP2/AN2
GP4/AN3
Converter
REF
(ADC)
CHS
V
REF
allows
V
DD
GO/DONE
VCFG = 0
VCFG = 1
The ADC voltage reference is software selectable to
either V
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 9-1 shows the block diagram of the ADC.
9.1.2
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
ADON
A/D
DD
or a voltage applied to the external reference
CHANNEL SELECTION
ADFM
ADRESH ADRESL
0 = Left Justify
1 = Right Justify
PIC12F683
10
10
DS41211C-page 61

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