PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 103
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
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13.0
FIGURE 13-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
SOSCO/T1CK
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
2: Some registers and associated bits
SOSCI
TIMER1
T1IF
Event Flag
Configuration Word DEVCFG1.
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 14. “Timers” (DS61105)
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
of the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
TGATE (T1CON<7>)
TIMER1 BLOCK DIAGRAM
0
1
Reset
Equal
SOSCEN
16-bit Comparator
TMR1
PR1
PBCLK
in
Q
Q
(1)
Gate
Sync
D
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can oper-
ate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Secondary Oscillator (S
for real-time clock applications. The following modes
are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
• Asynchronous mode can be used with the S
registers
to function as a Real-Time Clock (RTC)
PIC32MX3XX/4XX
Additional Supported Features
1 0
x 1
0 0
TSYNC (T1CON<2>)
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
0
1
1, 8, 64, 256
(T1CON<5:4>)
Prescaler
TCKPS<1:0>
Sync
DS61143H-page 103
2
OSC
OSC
)
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