PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 71
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
- Current page: 71 of 214
- Download datasheet (5Mb)
TABLE 4-23:
TABLE 4-24:
Legend:
Note
Legend:
Note
6080
6090
60A0
60B0
6080
6090
60A0
60B0
1:
1:
PORTC
PORTC
TRISC
TRISC
ODCC
ODCC
LATC
LATC
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORTC REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY
PORTC REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H
DEVICES ONLY
TRISC15
ODCC15
TRISC15
ODCC15
LATC15
LATC15
31/15
31/15
RC15
RC15
—
—
—
—
—
—
—
—
TRISC14
TRISC14
ODCC14
ODCC14
LATC14
LATC14
30/14
30/14
RC14
RC14
—
—
—
—
—
—
—
—
(1)
TRISC13
ODCC13
TRISC13
ODCC13
LATC13
LATC13
29/13
29/13
RC13
RC13
—
—
—
—
—
—
—
—
TRISC12
ODCC12
TRISC12
ODCC12
LATC12
LATC12
28/12
RC12
28/12
RC12
—
—
—
—
—
—
—
—
27/11
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24/8
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
Bits
23/7
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
TRISC4
ODCC4
LATC4
20/4
20/4
RC4
—
—
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
TRISC3
ODCC3
LATC3
19/3
RC3
19/3
—
—
—
—
—
—
—
—
—
—
—
—
TRISC2
ODCC2
LATC2
18/2
RC2
18/2
—
—
—
—
—
—
—
—
—
—
—
—
TRISC1
ODCC1
LATC1
17/1
RC1
17/1
—
—
—
—
—
—
—
—
—
—
—
—
16/0
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
for more
for more
0000
F01E
0000
xxxx
0000
xxxx
0000
0000
0000
F000
0000
xxxx
0000
xxxx
0000
0000
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