PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 78
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
- Current page: 78 of 214
- Download datasheet (5Mb)
TABLE 4-37:
TABLE 4-38:
Legend:
Note
Legend:
7000
7010 PMMODE
7020 PMADDR
7030 PMDOUT
7040
7050
7060
F200
1:
PMSTAT
DDPCON
PMCON
PMAEN
PMDIN
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0 CS2EN/A15 CS1EN/A14
15:0
15:0
15:0
15:0
31:16
15:0
PARALLEL MASTER PORT REGISTERS MAP
PROGRAMMING AND DIAGNOSTICS REGISTERS MAP
31/15
BUSY
ON
IBF
31/15
—
—
—
—
—
—
—
30/14
IBOV
30/14
—
—
—
—
—
—
IRQM<1:0>
—
—
29/13
SIDL
29/13
—
—
—
—
—
—
—
—
28/12
28/12
ADRMUX<1:0>
—
—
—
—
—
—
—
—
INCM<1:0>
27/11
IB3F
27/11
—
—
—
—
—
—
—
PMPTTL
MODE16
26/10
IB2F
26/10
—
—
—
—
—
—
—
(1)
PTWREN
25/9
IB1F
25/9
—
—
—
—
—
MODE<1:0>
—
—
PTRDEN
DATAOUT<31:0>
24/8
IB0F
DATAIN<31:0>
24/8
—
—
—
—
—
PTEN<15:0>
—
—
Bits
Bits
23/7
OBE
23/7
—
—
—
—
—
ADDR<13:0>
WAITB<1:0>
—
—
CSF<1:0>
OBUF
22/6
22/6
—
—
—
—
—
—
—
21/5
ALP
21/5
—
—
—
—
—
—
—
—
CS2P
20/4
20/4
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
WAITM<3:0>
—
—
JTAGEN
CS1P
OB3E
19/3
19/3
—
—
—
—
—
—
TROEN
OB2E
18/2
18/2
—
—
—
—
—
—
—
WRSP
OB1E
17/1
17/1
—
—
—
—
—
—
—
WAITE<1:0>
RDSP
OB0E
16/0
16/0
for more
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
008F
0000
0008
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