PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 82
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
- Current page: 82 of 214
- Download datasheet (5Mb)
TABLE 4-43:
Legend:
Note
5040
5050
5060
5070
5080 U1PWRC
5200
5210
5220
5230
5240 U1STAT
5250
5260
5270 U1BDTP1
1:
2:
3:
4:
U1ADDR
U1OTG
U1OTG
U1OTG
U1OTG
U1CON
STAT
U1IR
U1EIR
U1EIE
U1IE
CON
IR
IE
(2)
(2)
(3)
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
Registers”
This register does not have associated CLR, SET, and INV registers.
All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported.
The reset value for this bit is undefined.
(3)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
USB REGISTERS MAP
for more information.
31/15
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(1)
28/12
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26/10
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25/9
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24/8
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UACTPND
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
JSTATE
STALLIF
STALLIE
LSPDEN
BTSEF
BTSEE
Bits
23/7
IDIF
IDIE
—
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ID
—
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—
(4)
(4)
T1MSECIF LSTATEIF
T1MSECIE LSTATEIE
ATTACHIF RESUMEIF
ATTACHIE RESUMEIE
BMXEF
BMXEE
SE0
22/6
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—
ENDPT<3:0>
(4)
TOKBUSY
LSTATE
DMAEF
DMAEE
PKTDIS
21/5
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—
—
—
—
—
—
(4)
BDTPTRL<7:1>
USLPGRD
USBRST
ACTVIE
ACTVIF
BTOEE
IDLEIF
IDLEIE
BTOEF
20/4
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—
DEVADDR<6:0>
SESVDIF SESENDIF
SESVDIE SESENDIE
HOSTEN
DFN8EF
DFN8EE
SESVD
TRNIF
TRNIE
19/3
DIR
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CRC16EF
CRC16EE
RESUME
SESEND
OTGEN
SOFIF
SOFIE
Section 12.1.1 “CLR, SET and INV
18/2
PPBI
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USUSPEND USBPWR 0000
VBUSCHG VBUSDIS 0000
CRC5EF
CRC5EE
PPBRST
UERRIF
UERRIE
EOFEF
EOFEE
17/1
—
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—
—
—
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—
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—
—
VBUSVDIE 0000
VBUSVDIF 0000
DETACHIF 0000
DETACHIE 0000
VBUSVD 0000
URSTIF
URSTIE
USBEN
SOFEN
PIDEF
PIDEE
16/0
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0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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