DS26514GN+ Maxim Integrated Products, DS26514GN+ Datasheet - Page 254
DS26514GN+
Manufacturer Part Number
DS26514GN+
Description
IC TXRX T1/E1/J1 4PORT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS26514GN.pdf
(305 pages)
Specifications of DS26514GN+
Number Of Drivers/receivers
4/4
Protocol
Ethernet
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: BERT Receive All-Ones Condition (BRA1). This bit is set when 32 consecutive ones are received and
clears when at least one zero is received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). This bit is set when 32 consecutive zeros are received and
clears when at least one “one” is received.
Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS). This bit is set whenever the receive BERT
begins searching for a pattern and clears when BERT enter SYNC condition.
Bit 0: BERT in Synchronization Condition (BSYNC). This bit is set when the incoming pattern matches for 32
consecutive bit positions and remains set until the BERT enters Loss of Synchronization condition.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
All latched bits in this register can create interrupts.
Bit 7: BERT Receive All-Ones Condition Clear (BRA1C). A latched bit, which is set when the BERT transitions
out of All-Ones Condition.
Bit 6: BERT Receive All-Zeros Condition Clear (BRA0C). A latched bit, which is set when the BERT transitions
out of All-Zeros Condition.
Bit 5: BERT Receive Loss Of Synchronization Condition Clear (BRLOSC). A latched bit which is set when the
BERT transitions out of Loss Of Synchronization Condition.
Bit 4: BERT in Synchronization Condition Clear (BSYNCC). A latched bit that is set when the BERT transitions
out of Synchronization Condition.
Bit 3: BERT Receive All-Ones Condition Detect (BRA1D). A latched bit, which is set when 32 consecutive ones
are received.
Bit 2: BERT Receive All-Zeros Condition Detect (BRA0D). A latched bit, which is set when 32 consecutive zeros
are received.
Bit 1: BERT Receive Loss Of Synchronization Condition Detect (BRLOSD). A latched bit which is set
whenever the receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition Detect (BSYNCD). A latched bit that is set when the incoming pattern
matches for 32 consecutive bit positions.
Register Name:
Rev: 101608
BRA1C
7
0
7
0
-
BRA0C
BRSR
Bert Real-Time Status Register
1401h + (10h x (n-1)) : where n = 1 to 4
BLSR1
BERT Latched Status Register 1
1402h + (10h x (n-1)) : where n = 1 to 4
BSIM1
6
0
6
0
-
BRLOSC
5
0
5
0
-
BSYNCC
4
0
4
0
-
BRA1D
BRA1
3
0
3
0
BRA0D
BRA0
2
0
2
0
DS26514 4-Port T1/E1/J1 Transceiver
BRLOS
BRLOS
D
1
0
1
0
BSYNCD
BSYNC
0
0
0
0
254 of 305
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