DS26334GNA3+ Maxim Integrated Products, DS26334GNA3+ Datasheet - Page 84
DS26334GNA3+
Manufacturer Part Number
DS26334GNA3+
Description
IC LIU E1/T1/J1 3.3V 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS26334G.pdf
(121 pages)
Specifications of DS26334GNA3+
Number Of Drivers/receivers
16/16
Protocol
IEEE 1149.1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLK for Channel n is
disabled upon a loss of signal and set as a low output. When reset or default RCLK will switch to MCLK upon a
loss of signal within 10ms.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: INT Pin Mode (INTM). This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
Bit 0: Clear On Write Enable (CWE). When this bit is set the clear on write is enabled for all the latched interrupt
status registers. The host processor must write a 1 to the latched interrupt status register bit position before the
particular bit will be cleared. Default for all the latched interrupt status registers is to clear on a read.
0 = Pin is high impedance when not active.
1 = Pin drives high when not active.
RDULR16
RDULR8
—
7
0
7
0
7
0
RDULR15
RDULR7
—
6
0
6
0
6
0
RDULR
RCLK Disable Upon LOS Register
16h
36h
GISC
Global Interrupt Status Control Register
1Eh
RDULR14
RDULR6
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
—
5
0
5
0
5
0
RDULR13
RDULR5
84 of 121
—
4
0
4
0
4
0
RDULR12
RDULR4
—
3
0
3
0
3
0
RDULR11
RDULR3
—
2
0
2
0
2
0
RDULR10
RDULR2
INTM
1
0
1
0
1
0
RDULR1
RDULR9
CWE
0
0
0
0
0
0
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