ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 179
ST92F120V1Q7
Manufacturer Part Number
ST92F120V1Q7
Description
Microcontrollers (MCU) Flash 128K SPI/I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST92F120V9Q7.pdf
(325 pages)
Specifications of ST92F120V1Q7
Data Bus Width
8 bit, 16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
PQFP-100
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 16 Channel
Lead Free Status / Rohs Status
No
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10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5.1 Introduction
The Multiprotocol Serial Communications Inter-
face (SCI-M) offers full-duplex serial data ex-
change with a wide range of external equipment.
The SCI-M offers four operating modes: Asynchro-
nous, Asynchronous with synchronous clock, Seri-
al expansion and Synchronous.
10.5.2 Main Features
Figure 88. SCI-M Block Diagram
Full duplex synchronous and asynchronous
operation.
Transmit, receive, line status, and device
address interrupt generation.
Integral Baud Rate Generator capable of
dividing the input clock by any value from 2 to
2
16X data sampling clock for asynchronous
operation or the 1X clock for synchronous
operation.
Fully programmable serial interface:
– 5, 6, 7, or 8 bit word length.
– Even, odd, or no parity generation and detec-
– 0, 1, 1.5, 2, 2.5, 3 stop bit generation.
– Complete status reporting capabilities.
– Line break generation and detection.
16
tion.
-1 (16 bit word) and generating the internal
SOUT
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
TRANSMIT
REGISTER
TRANSMIT
REGISTER
BUFFER
SHIFT
RTS
CONTROLLER
SDS
DMA
TXCLK/CLKOUT RXCLK
ST9 CORE BUS
Frame Control
ALTERNATE
COMPARE
ADDRESS
and STATUS
REGISTER
FUNCTION
GENERATOR
CLOCK and
BAUD RATE
CONTROLLER
DMA
– Local loopback for communications link fault
– Auto-echo for communications link fault isola-
– High speed communication
– Possibility of hardware synchronization (RTS/
– Programmable polarity and stand-by level for
– Programmable active edge and stand-by level
– Programmable active levels of RTS/DCD sig-
– Full Loop-Back and Auto-Echo modes for DA-
Programmable address indication bit (wake-up
bit) and user invisible compare logic to support
multiple microcomputer networking. Optional
character search function.
Internal diagnostic capabilities:
Separate interrupt/DMA channels for transmit
and receive.
In addition, a Synchronous mode supports:
DCD
RECEIVER
REGISTER
RECEIVER
REGISTER
BUFFER
isolation.
tion.
DCD signals).
data SIN/SOUT.
for clocks CLKOUT/RXCL.
nals.
TA, CLOCKs and CONTROLs.
SHIFT
SIN
VA00169A
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