ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 72
ST92F120V1Q7
Manufacturer Part Number
ST92F120V1Q7
Description
Microcontrollers (MCU) Flash 128K SPI/I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST92F120V9Q7.pdf
(325 pages)
Specifications of ST92F120V1Q7
Data Bus Width
8 bit, 16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
PQFP-100
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 16 Channel
Lead Free Status / Rohs Status
No
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ST92F120 - INTERRUPTS
ARBITRATION MODES (Cont’d)
5.5.2 Nested Mode
The difference between Nested mode and Con-
current mode, lies in the modification of the Cur-
rent Priority Level (CPL) during interrupt process-
ing.
The arbitration phase is basically identical to Con-
current mode, however, once the request is ac-
knowledged, the CPL is saved in the Nested Inter-
rupt Control Register (NICR) by setting the NICR
bit corresponding to the CPL value (i.e. if the CPL
is 3, the bit 3 will be set).
The CPL is then loaded with the priority of the re-
quest just acknowledged; the next arbitration cycle
is thus performed with reference to the priority of
the interrupt service routine currently being exe-
cuted.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
Figure 34. Simple Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN unchanged by the interrupt routines
72/324
9
0
1
2
3
4
5
6
7
Priority Level of
Interrupt Request
CPL is set to 7
INT5
MAIN
ei
CPL=5
INT 5
INT2
INT3
INT4
CPL=2
INT 2
INT0
CPL=0
INT 0
CPL2 < CPL4:
Serviced next
CPL=3
INT 3
INT6
CPL6 > CPL3:
INT6 pending
CPL=4
– All maskable interrupt requests are disabled by
– CPL is saved in the special NICR stack to hold
– Priority level of the acknowledged routine is
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
– If ENCSR is set, CSR is loaded with ISR con-
INT 4
INT2
clearing CICR.IEN.
the priority level of the suspended routine.
stored in CPL, so that the next request priority
will be compared with the one of the routine cur-
rently being serviced.
stack.
the Vector Table, pointed to by the IVR.
tents; otherwise ISR is used in place of CSR until
iret instruction.
CPL=2
INT 2
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
CPL=6
INT 6
CPL=7
MAIN
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