MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 331
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
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The write cycle timing diagram is shown in
Table 17-4
17.5.5 Fast Termination Cycles
Two clock cycle transfers are supported on the MCF5235 bus. In most cases, this is impractical to
use in a system because the termination must take place in the same half-clock during which TS
is asserted. As this is atypical, it is not referred to as the zero-wait-state case but is called the
fast-termination case. Fast termination cycles occur when the external device or memory asserts
TA less than one clock after TS is asserted. This means that the MCF5235 samples TA on the rising
Freescale Semiconductor
A[31:0], TSIZ[1:0]
describes the six states of a basic write cycle.
1.
2.
3.
4.
5.
6.
1.
2.
1.
CSn, BSn
CLKOUT
Set R/W to write
Place address on A[31:0]
Assert TIP and TSIZ[1:0]
Assert TS
Place data on D[31:0]
Negate TS
Sample TA low
Stop driving data from D[31:0]
Start next cycle
D[31:0]
R/W
TIP
TS
TA
MCF5235
Figure 17-8. Basic Write Bus Cycle
Figure 17-7. Write Cycle Flowchart
MCF5235 Reference Manual, Rev. 2
S0
Figure
S1
17-8.
S2
Write
1.
2.
3.
1.
S3
Decode address
Store data on D[31:0]
Assert TA
Negate TA
S4
System
S5
Data Transfer Operation
17-9
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