MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 45
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 45 of 754
- Download datasheet (13Mb)
1.3
1.3.1
Freescale Semiconductor
• Version 2 ColdFire variable-length RISC processor core
• Enhanced Time Processor Unit (eTPU)
• System debug support
• On-chip memories
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at twice the internal bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support
— Illegal instruction decode that allows for 68K emulation support
— Event triggered VLIW processor timer subsystem
— 32 channels
— 24-bit timer resolution
— 6 Kbyte of code memory and 1.5 Kbyte of data memory
— Variable number of parameters allocatable per channel
— Double match/capture channels
— Angle mode support
— Interrupt request support
— Debug support
— Integrated debug supports both ColdFire debug and eTPU debug features on a single
— Unified programming model including both ColdFire and eTPU debug registers
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and
— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
Features
Feature Overview
support the user stack pointer register, and 4 new instructions for improved bit
processing
32-bit signal processing algorithms
port with cross triggering operations for ease of use
address with optional data) that can be configured into a 1- or 2-level trigger
MCF5235 Reference Manual, Rev. 2
Features
1-5
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