DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 35
DS1878T+T&R
Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet
1.DS1878TTR.pdf
(98 pages)
Specifications of DS1878T+T&R
Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
Read
Access
Write
Access
ACCESS
80–9F
00–FF
(HEX)
80–9F
(HEX)
(HEX)
ROW
ROW
ROW
CODE
A0
A0
<5>
<8>
<8>
<8>
<8>
separately
See each
NAME
NAME
NAME
ROW
ROW
ROW
bit/byte
SFP+ Controller with Digital LDD Interface
AUX EE
LUT7
LUT7
LUT8
LUT8
<0>
______________________________________________________________________________________
BYTE 0/8
BYTE 0/8
BYTE 0/8
PW2
<1>
DAC1
DAC1
DAC2
DAC2
All
EE
WORD 0
WORD 0
WORD 0
<2>
N/A
All
BYTE 1/9
BYTE 1/9
BYTE 1/9
DAC1
DAC1
DAC2
DAC2
EE
hardware
All and
device
<3>
All
AUXILIARY MEMORY (A0h)
BYTE 2/A
BYTE 2/A
BYTE 2/A
TABLE 07h (DAC1 LUT)
TABLE 08h (DAC2 LUT)
DAC1
DAC1
DAC2
DAC2
PW2 +
mode
EE
PW2
<4>
bit
WORD 1
WORD 1
WORD 1
BYTE 3/B
BYTE 3/B
BYTE 3/B
<5>
All
All
DAC1
DAC1
DAC2
DAC2
EE
<6>
N/A
All
Auxiliary A0h Memory Register Map
RESERVED
RESERVED
BYTE 4/C
BYTE 4/C
BYTE 4/C
DAC1
DAC2
EE
PW1
PW1
<7>
WORD 2
WORD 2
WORD 2
RESERVED RESERVED
RESERVED RESERVED
BYTE 5/D
BYTE 5/D
BYTE 5/D
DAC1
DAC2
PW2
PW2
<8>
Table 07h Register Map
Table 08h Register Map
EE
PW2
<9>
N/A
BYTE 6/E
BYTE 6/E
BYTE 6/E
DAC1
DAC2
EE
WORD 3
WORD 3
WORD 3
<10>
PW2
N/A
RESERVED
RESERVED
BYTE 7/F
BYTE 7/F
BYTE 7/F
DAC1
DAC2
EE
<11>
PW1
All
35
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