SCAN25100TYA/NOPB National Semiconductor, SCAN25100TYA/NOPB Datasheet - Page 17

IC SERIAL/DESERIAL CPRI 100-TQFP

SCAN25100TYA/NOPB

Manufacturer Part Number
SCAN25100TYA/NOPB
Description
IC SERIAL/DESERIAL CPRI 100-TQFP
Manufacturer
National Semiconductor
Series
SCANr
Datasheet

Specifications of SCAN25100TYA/NOPB

Function
Serializer/Deserializer
Data Rate
2.5Gbps
Input Type
LVTTL/LVCMOS
Output Type
LVTTL, LVCMOS
Number Of Inputs
10
Number Of Outputs
10
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
TQFP EP
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SCAN25100TYA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SCAN25100TYA/NOPB
Manufacturer:
NS
Quantity:
158
Part Number:
SCAN25100TYA/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Receive Equalization
The receiver front-end provides 3 steps of equalization filter
to compensate for ISI deterministic jitter from lossy back-
Receive Output Bus
Receive output data ROUT[9:0] is clocked on both rising and
falling edges of RXCLK. By using both RXCLK edges, the
RXPWDNB
Rx Output
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
ROUT[8]
ROUT[9]
EQ[1]
0
0
1
1
0
1
1
1
Missing REFCLK & in 10B
EQ[0]
Not Locked
TABLE 11. Receiver Output Truth Table (10-bit Mode, TENBMODE = 1)
Rx PLL
Locked
0
1
0
1
mode
x
10-bit Mode (TENBMODE = 1)
TABLE 10. Receiver Parallel Output Bus Mapping
Equalization disabled.
Equalization (approximately 2 dB).
Equalization (approximately 4 dB).
Equalization (approximately 8 dB).
FIGURE 4. SCAN25100 Serial Input Connection
TABLE 9. Receiver Equalizer Control Settings
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
Coded Data Bit
running at DDR Rate
Based on REFCLK
Recovered Clock
RXCLK
High - Z
High - Z
17
planes and cables. Pulling both EQ[1:0] pins low enables
MDIO control of equalization.
clock speed is halved, which reduces EMI issues. The re-
ceiver output bus can be configured in either read or write
mode.
30.72 MHz based on
30.72 MHz based on
Descriptions
Undefined
SYSCLK
REFCLK
High - Z
RXCLK
8-bit Mode (TENBMODE = 0)
Line Code Error Flag
Data Bit 7 (H, msb)
Data Bit 0 (A, lsb)
Data Bit 6 (G)
Data Bit 1 (B)
Data Bit 2 (C)
Data Bit 3 (D)
Data Bit 4 (E)
Data Bit 5 (F)
D/K Flag (Z)
Deserialized 10-bit Word
1111111111
ROUT[9:0]
Undefined
High - Z
20183471
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