FIN1218MTDX Fairchild Semiconductor, FIN1218MTDX Datasheet
FIN1218MTDX
Specifications of FIN1218MTDX
FIN1218MTDXTR
Related parts for FIN1218MTDX
FIN1218MTDX Summary of contents
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... Part Number Temperature Range FIN1215MTDX FIN1216MTDX - 85°C FIN1217MTDX FIN1218MTDX (Preliminary) For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Description The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low-Voltage TTL) data into three serial ...
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... Figure 1. FIN1217 / FIN1215 Transmitter Functional Diagram Figure 2. FIN1218 / FIN1216 Receiver Functional Diagram Table 1. Serializers / De-Serializers Chip Matrix CLK Part Frequency FIN1215 66 FIN1216 66 FIN1217 85 FIN1218 85 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 LVTTL IN LVDS OUT LVDS LVTTL Package OUT 48-Lead TSSOP ...
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... GND © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Figure 3. FIN1217 / FIN1215 (21:3 Transmitter) Description of Signals LVTTL Level Inputs LVTTL Level Clock Input; the rising edge is for data strobe Positive LVDS Differential Data Output Negative LVDS Differential Data Output ...
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... GND © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Figure 4. FIN1216 / FIN1218 (3:21 Receiver) Description of Signals Negative LVDS Differential Data Output Positive LVDS Differential Data Output Negative LVDS Differential Clock Output Positive LVDS Differential Clock Output LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW LVTTL Level Clock Output LVTTL Level Input ...
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... Failsafe condition is defined as the input being terminated and un-driven, shorted, or open RxCLKIn± is removed prior to the RxIn± date being removed, RxOut is the last valid state. If RxIn± data is removed prior to RxCLKIn± being removed, RxOut is HIGH. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (1) PwrDn TxOut± ...
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... Note: 6. 100mV V noise should be tested for frequency at least up to 2MHz. All the specifications should be met under CC such a noise level. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Parameter LVDS I/O to Ground All Pins (FIN1215, FIN1217) FIN1215, FIN1217 Only ...
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... The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. 10. FIN1217 only. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 =3.3V; minimum and maximum are at over supply voltages and operating ...
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... TPPB3 t Transmitter Output Pulse Position of Bit 4 TPPB4 t Transmitter Output Pulse Position of Bit 5 TPPB5 t Transmitter Output Pulse Position of Bit 6 TPPB6 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Conditions Figure 10 10% to 90% Figure 11 Figure 8 Figure 10 f=85MHz FIN1217 only (11) ...
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... MSB is output from transmitter. 13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter of less than 2ns. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Conditions Min ...
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... The power supply current for the receiver can be different due to the number of active I/O channels. 15. 85MHz specification for FIN1218 only. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 =3.3V. Positive current values refer to the current flowing into device and ...
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... RSPB3 t Receiver Input Strobe Position of Bit 4 RSPB4 t Receiver Input Strobe Position of Bit 5 RSPB5 t Receiver Input Strobe Position of Bit 6 RSPB6 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Conditions Min. Typ. 10.0 11.0 Figure 12 10.0 12.2 Rising Edge Strobe 6 ...
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... Receiver Phase Lock Loop Set Time RPLLS Notes: 16. Total channel latency from serializer to deserializer 17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Conditions Figure 21 f=65MHz ...
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... Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages ( 1.25 1.15 2.40 2.30 0.10 0 1.50 0.90 2.40 1.80 0.60 0 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 <=1ns. F Resulting Differential Input Voltage (mV 1.15 1.25 2.30 2.40 0 0.10 0.90 1.50 1 ...
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... Figure 8. Transmitter LVDS Output Load and Transition Times Figure 9. Receiver LVTTL/CMOS Output Load and Transition Times Figure 10. Transmitter Set-up/Hold and HIGH/LOW Times (Rising Edge Strobe) Figure 11. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Figure 7. Worst-Case Test Pattern Transmitter Input Clock Transition Time 14 ...
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... AC Loadings and Waveforms Figure 12. Figure 13. Figure 14. Figure 15. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Receiver Set-up/Hold and HIGH/LOW Times Transmitter Clock-In to Clock-Out Delay (Rising Edge Strobe) Receiver Clock-In to Clock-Out Delay (Rising Edge Strobe) Transmitter Phase-Lock-Loop Set Time 15 www ...
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... Note: This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter. Figure 19. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Figure 16 ...
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... AC Loadings and Waveforms Figure 20. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued)] Transmitter Output Pulse Bit Position Figure 21. Receiver Strobe Bit Position 17 www.fairchildsemi.com ...
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... The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross V with 100mV noise (V © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Figure 22. ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 20 www.fairchildsemi.com ...