PI2EQX5804CNJE Pericom Semiconductor, PI2EQX5804CNJE Datasheet - Page 11
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PI2EQX5804CNJE
Manufacturer Part Number
PI2EQX5804CNJE
Description
IC PCI-E REDRIVER 100LBGA
Manufacturer
Pericom Semiconductor
Series
ReDriver™r
Type
Redriverr
Datasheet
1.PI2EQX5804CNJE.pdf
(23 pages)
Specifications of PI2EQX5804CNJE
Tx/rx Type
CML
Capacitance - Input
50pF
Voltage - Supply
1.15 V ~ 1.25 V
Current - Supply
800mA
Mounting Type
Surface Mount
Package / Case
100-LBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Delay Time
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI2EQX5804CNJE
Manufacturer:
Pericom
Quantity:
1 453
Part Number:
PI2EQX5804CNJE
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI2EQX5804CNJEX
Manufacturer:
PERICOM
Quantity:
20 000
Addressing
Up to eight PI2EQX5804C devices can be connected to a single I
addressing, with the LSB indicating either a read or write operation. The address for a specifi c device is deter-
mined by the A0, A1 and A4 input pins.
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH)
during the acknowledge clock pulse, the PI2EQX5804C will pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I
Data Transfer diagram. The PI2EQX5804C will generate an acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5804C
will watch the next byte of information for a match with its address setting. When a match is found it will
respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge
bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the fi rst data byte fol-
lowing the address byte is a dummy or fi ll byte that is not used by the PI2EQX5804C. This byte is provided
to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
signifi cant bit (MSB) fi rst. After each block write, address pointer will reset to byte 0.
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most signifi cant bit (MSB) fi rst (see the I
PI2EQX5804C will never hold the clock line SCL LOW to force the master into a wait state.
Note: Byte-write and byte-read transfers have a fi xed offset of 0x00, because of the very small number of con-
fi guration bytes. An offset byte presented by a host to the PI2EQX5804C is not used.
A6
1
09-0001
Address Assignment
A5
1
Program
A4
A3
0
11
A2
0
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
2
C bus. The PI2EQX5804C supports 7-bit
2
C Data Transfer diagram). The
A1
Programmable
Equalization & Emphasis
A0
PS8926B
PI2EQX5804C
1=R, 0=W
R/W
2
06/08/09
C