PCA9558PW,118 NXP Semiconductors, PCA9558PW,118 Datasheet - Page 9

• Manufacturer Part Number: PCA9558PW,118
• Description: IC I2C SMBUS 8BIT I/O 28TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9558PW,118

• Package / Case: 28-TSSOP
• Applications: PC's, PDA's
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Logic Family: PCA9558
• Number Of Lines (input / Output): 8.0 / 8.0
• Propagation Delay Time: 21 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: 0 C to + 70 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935269433118; PCA9558PW-T; PCA9558PW-T

NXP Semiconductors
PCA9558_4
Product data sheet
7.1.2.2 OP - Output Port register
7.1.2.3 PI - Polarity Inversion register
7.1.2.4 IOC - Input/Output Configuration register
This register is an output-only port. It reflects the outgoing logic levels of the GPIO defined
as outputs in the IOC register. Bit values in this register have no effect on GPIO defined as
inputs. In turn, reads from this register reflect the value stored in the flip-flop controlling
the output, not the actual output value.
Table 6.
This register enables polarity inversion of GPIO defined as inputs by the IOC register. If a
bit in this register is set to a logic 1, the corresponding GPIO input port is inverted. If a bit
in this register is set to a logic 0, the corresponding GPIO input port is not inverted.
Table 7.
This register configures the direction of the GPIO pins (IOx). If a bit is set to a logic 1, the
corresponding port pin is enabled as an input with a high-impedance output driver. If a bit
is set to a logic 0, the corresponding port pin is enabled as an output.
Table 8.
Examples of read/write to these registers can be found in
and
The IO_OUT_LOW input, when held LOW longer than the time T
registers to their default (power-up) values.
A read of the present value of the inputs MUX_INx can be done via the I
done by addressing the PCA9558 in a write mode and entering the correct command
code. The preset value on the MUX_INx inputs is latched at the command code
Acknowledge. A REPEATED START is then sent with the R/W bit set to a logic 1, read,
and this latched data is read out on the I
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Figure
OP - Output Port register description
PI - Polarity Inversion register description
IOC - Input/Output Configuration register description
16.
O7
C7
P7
7
0
7
1
7
1
O6
P6
C6
Rev. 04 — 14 April 2009
6
0
6
1
6
1
O5
P5
C5
5
0
5
1
5
1
2
C-bus. See
O4
C4
P4
4
0
4
1
4
1
O3
P3
C3
Figure
3
0
3
0
3
1
Figure
8-bit I
11.
O2
C2
P2
2
2
2
0
0
1
cy(W)
9,
2
C-bus/SMBus I/O port
Figure
, will reset the GPIO
PCA9558
© NXP B.V. 2009. All rights reserved.
2
O1
P1
C1
C-bus. This is
1
0
1
0
1
1
10,
Figure
O0
C0
P0
0
0
0
0
0
1
9 of 27
15,