PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 5
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PI7C8150AMAE
Manufacturer Part Number
PI7C8150AMAE
Description
IC PCI-PCI BRIDGE 2PORT 208-FQFP
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150ANDE.pdf
(111 pages)
Specifications of PI7C8150AMAE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
208-FQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
06-0057
TABLE OF CONTENTS
1
2
3
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
2.2.1
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.7.1
3.7.2
3.7.3
3.7.4
3.8.1
3.8.2
3.8.3
3.8.4
INTRODUCTION................................................................................................. 11
SIGNAL DEFINITIONS...................................................................................... 12
PCI BUS OPERATION........................................................................................ 21
3.8.3.1
3.8.3.2
3.8.3.3
3.8.4.1
S
S
PIN LIST – 208-PIN FQFP .......................................................................................................... 18
PIN LIST – 256-BALL PBGA ..................................................................................................... 20
TYPES OF TRANSACTIONS..................................................................................................... 22
SINGLE ADDRESS PHASE ....................................................................................................... 22
DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 23
DATA PHASE ............................................................................................................................. 23
WRITE TRANSACTIONS .......................................................................................................... 23
READ TRANSACTIONS............................................................................................................ 27
CONFIGURATION TRANSACTIONS ...................................................................................... 30
TRANSACTION TERMINATION ............................................................................................. 34
IGNAL
IGNALS
PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12
CLOCK SIGNALS ............................................................................................................... 15
MISCELLANEOUS SIGNALS........................................................................................... 16
GENERAL PURPOSE I/O INTERFACE SIGNALS ........................................................ 17
JTAG BOUNDARY SCAN SIGNALS ................................................................................ 17
POWER AND GROUND..................................................................................................... 17
MEMORY WRITE TRANSACTIONS................................................................................ 23
MEMORY WRITE AND INVALIDATE ............................................................................ 24
DELAYED WRITE TRANSACTIONS............................................................................... 25
WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 26
BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 26
FAST BACK-TO-BACK TRANSACTIONS ....................................................................... 26
PREFETCHABLE READ TRANSACTIONS.................................................................... 27
NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 27
READ PREFETCH ADDRESS BOUNDARIES ............................................................... 28
DELAYED READ REQUESTS .......................................................................................... 28
DELAYED READ COMPLETION WITH TARGET ........................................................ 29
DELAYED READ COMPLETION ON INITIATOR BUS................................................ 29
FAST BACK-TO-BACK READ TRANSACTION ............................................................. 30
TYPE 0 ACCESS TO PI7C8150A....................................................................................... 31
TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 31
TYPE 1 TO TYPE 1 FORWARDING................................................................................. 33
SPECIAL CYCLES ............................................................................................................. 34
MASTER TERMINATION INITIATED BY PI7C8150A ................................................. 35
MASTER ABORT RECEIVED BY PI7C8150A ................................................................ 36
TARGET TERMINATION RECEIVED BY PI7C8150A.................................................. 36
TARGET TERMINATION INITIATED BY PI7C8150A.................................................. 39
DELAYED WRITE TARGET TERMINATION RESPONSE........................................ 37
POSTED WRITE TARGET TERMINATION RESPONSE ........................................... 37
DELAYED READ TARGET TERMINATION RESPONSE ......................................... 38
TARGET RETRY ............................................................................................................ 39
T
........................................................................................................................................ 12
YPES
............................................................................................................................... 12
Page 5 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A